1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * Configuration settings for the TI OMAP3530 Beagle board. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 /* 32 * High Level Configuration Options 33 */ 34 #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ 35 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 36 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 37 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 38 #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ 39 40 #define CONFIG_SDRC /* The chip has SDRC controller */ 41 42 #include <asm/arch/cpu.h> /* get chip and board defs */ 43 #include <asm/arch/omap3.h> 44 45 /* 46 * Display CPU and Board information 47 */ 48 #define CONFIG_DISPLAY_CPUINFO 1 49 #define CONFIG_DISPLAY_BOARDINFO 1 50 51 /* Clock Defines */ 52 #define V_OSCK 26000000 /* Clock output from T2 */ 53 #define V_SCLK (V_OSCK >> 1) 54 55 #undef CONFIG_USE_IRQ /* no support for IRQs */ 56 #define CONFIG_MISC_INIT_R 57 58 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 59 #define CONFIG_SETUP_MEMORY_TAGS 1 60 #define CONFIG_INITRD_TAG 1 61 #define CONFIG_REVISION_TAG 1 62 63 /* 64 * Size of malloc() pool 65 */ 66 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 67 /* Sector */ 68 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 69 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 70 /* initial data */ 71 72 /* 73 * Hardware drivers 74 */ 75 76 /* 77 * NS16550 Configuration 78 */ 79 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 80 81 #define CONFIG_SYS_NS16550 82 #define CONFIG_SYS_NS16550_SERIAL 83 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 84 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 85 86 /* 87 * select serial console configuration 88 */ 89 #define CONFIG_CONS_INDEX 3 90 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 91 #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ 92 93 /* allow to overwrite serial and ethaddr */ 94 #define CONFIG_ENV_OVERWRITE 95 #define CONFIG_BAUDRATE 115200 96 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 97 115200} 98 #define CONFIG_GENERIC_MMC 1 99 #define CONFIG_MMC 1 100 #define CONFIG_OMAP_HSMMC 1 101 #define CONFIG_DOS_PARTITION 1 102 103 /* DDR - I use Micron DDR */ 104 #define CONFIG_OMAP3_MICRON_DDR 1 105 106 /* USB */ 107 #define CONFIG_MUSB_UDC 1 108 #define CONFIG_USB_OMAP3 1 109 #define CONFIG_TWL4030_USB 1 110 111 /* USB device configuration */ 112 #define CONFIG_USB_DEVICE 1 113 #define CONFIG_USB_TTY 1 114 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 115 116 /* commands to include */ 117 #include <config_cmd_default.h> 118 119 #define CONFIG_CMD_CACHE 120 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 121 #define CONFIG_CMD_FAT /* FAT support */ 122 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 123 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 124 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 125 #define MTDIDS_DEFAULT "nand0=nand" 126 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 127 "1920k(u-boot),128k(u-boot-env),"\ 128 "4m(kernel),-(fs)" 129 130 #define CONFIG_CMD_I2C /* I2C serial bus support */ 131 #define CONFIG_CMD_MMC /* MMC support */ 132 #define CONFIG_CMD_NAND /* NAND support */ 133 134 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 135 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 136 #undef CONFIG_CMD_IMI /* iminfo */ 137 #undef CONFIG_CMD_IMLS /* List all found images */ 138 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 139 #undef CONFIG_CMD_NFS /* NFS support */ 140 141 #define CONFIG_SYS_NO_FLASH 142 #define CONFIG_HARD_I2C 1 143 #define CONFIG_SYS_I2C_SPEED 100000 144 #define CONFIG_SYS_I2C_SLAVE 1 145 #define CONFIG_SYS_I2C_BUS 0 146 #define CONFIG_SYS_I2C_BUS_SELECT 1 147 #define CONFIG_DRIVER_OMAP34XX_I2C 1 148 149 /* 150 * TWL4030 151 */ 152 #define CONFIG_TWL4030_POWER 1 153 #define CONFIG_TWL4030_LED 1 154 155 /* 156 * Board NAND Info. 157 */ 158 #define CONFIG_SYS_NAND_QUIET_TEST 1 159 #define CONFIG_NAND_OMAP_GPMC 160 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 161 /* to access nand */ 162 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 163 /* to access nand at */ 164 /* CS0 */ 165 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 166 167 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 168 /* devices */ 169 #define CONFIG_JFFS2_NAND 170 /* nand device jffs2 lives on */ 171 #define CONFIG_JFFS2_DEV "nand0" 172 /* start of jffs2 partition */ 173 #define CONFIG_JFFS2_PART_OFFSET 0x680000 174 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 175 /* partition */ 176 177 /* Environment information */ 178 #define CONFIG_BOOTDELAY 10 179 180 #define CONFIG_EXTRA_ENV_SETTINGS \ 181 "loadaddr=0x82000000\0" \ 182 "usbtty=cdc_acm\0" \ 183 "console=ttyS2,115200n8\0" \ 184 "mpurate=500\0" \ 185 "vram=12M\0" \ 186 "dvimode=1024x768MR-16@60\0" \ 187 "defaultdisplay=dvi\0" \ 188 "mmcdev=0\0" \ 189 "mmcroot=/dev/mmcblk0p2 rw\0" \ 190 "mmcrootfstype=ext3 rootwait\0" \ 191 "nandroot=/dev/mtdblock4 rw\0" \ 192 "nandrootfstype=jffs2\0" \ 193 "mmcargs=setenv bootargs console=${console} " \ 194 "mpurate=${mpurate} " \ 195 "vram=${vram} " \ 196 "omapfb.mode=dvi:${dvimode} " \ 197 "omapfb.debug=y " \ 198 "omapdss.def_disp=${defaultdisplay} " \ 199 "root=${mmcroot} " \ 200 "rootfstype=${mmcrootfstype}\0" \ 201 "nandargs=setenv bootargs console=${console} " \ 202 "mpurate=${mpurate} " \ 203 "vram=${vram} " \ 204 "omapfb.mode=dvi:${dvimode} " \ 205 "omapfb.debug=y " \ 206 "omapdss.def_disp=${defaultdisplay} " \ 207 "root=${nandroot} " \ 208 "rootfstype=${nandrootfstype}\0" \ 209 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 210 "bootscript=echo Running bootscript from mmc ...; " \ 211 "source ${loadaddr}\0" \ 212 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 213 "mmcboot=echo Booting from mmc ...; " \ 214 "run mmcargs; " \ 215 "bootm ${loadaddr}\0" \ 216 "nandboot=echo Booting from nand ...; " \ 217 "run nandargs; " \ 218 "nand read ${loadaddr} 280000 400000; " \ 219 "bootm ${loadaddr}\0" \ 220 221 #define CONFIG_BOOTCOMMAND \ 222 "if mmc rescan ${mmcdev}; then " \ 223 "if run loadbootscript; then " \ 224 "run bootscript; " \ 225 "else " \ 226 "if run loaduimage; then " \ 227 "run mmcboot; " \ 228 "else run nandboot; " \ 229 "fi; " \ 230 "fi; " \ 231 "else run nandboot; fi" 232 233 #define CONFIG_AUTO_COMPLETE 1 234 /* 235 * Miscellaneous configurable options 236 */ 237 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 238 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 239 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 240 #define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # " 241 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 242 /* Print Buffer Size */ 243 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 244 sizeof(CONFIG_SYS_PROMPT) + 16) 245 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 246 /* Boot Argument Buffer Size */ 247 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 248 249 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 250 /* works on */ 251 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 252 0x01F00000) /* 31MB */ 253 254 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 255 /* load address */ 256 257 /* 258 * OMAP3 has 12 GP timers, they can be driven by the system clock 259 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 260 * This rate is divided by a local divisor. 261 */ 262 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 263 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 264 #define CONFIG_SYS_HZ 1000 265 266 /*----------------------------------------------------------------------- 267 * Stack sizes 268 * 269 * The stack sizes are set up in start.S using the settings below 270 */ 271 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 272 #ifdef CONFIG_USE_IRQ 273 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 274 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 275 #endif 276 277 /*----------------------------------------------------------------------- 278 * Physical Memory Map 279 */ 280 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 281 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 282 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 283 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 284 285 /* SDRAM Bank Allocation method */ 286 #define SDRC_R_B_C 1 287 288 /*----------------------------------------------------------------------- 289 * FLASH and environment organization 290 */ 291 292 /* **** PISMO SUPPORT *** */ 293 294 /* Configure the PISMO */ 295 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 296 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 297 298 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ 299 /* one chip */ 300 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 301 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 302 303 #define CONFIG_SYS_FLASH_BASE boot_flash_base 304 305 /* Monitor at start of flash */ 306 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 307 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 308 309 #define CONFIG_ENV_IS_IN_NAND 1 310 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 311 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 312 313 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 314 #define CONFIG_ENV_OFFSET boot_flash_off 315 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 316 317 /*----------------------------------------------------------------------- 318 * CFI FLASH driver setup 319 */ 320 /* timeout values are in ticks */ 321 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 322 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 323 324 /* Flash banks JFFS2 should use */ 325 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 326 CONFIG_SYS_MAX_NAND_DEVICE) 327 #define CONFIG_SYS_JFFS2_MEM_NAND 328 /* use flash_info[2] */ 329 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 330 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 331 332 #ifndef __ASSEMBLY__ 333 extern unsigned int boot_flash_base; 334 extern volatile unsigned int boot_flash_env_addr; 335 extern unsigned int boot_flash_off; 336 extern unsigned int boot_flash_sec; 337 extern unsigned int boot_flash_type; 338 #endif 339 340 /* additions for new relocation code, must be added to all boards */ 341 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 342 #define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE) 343 344 #endif /* __CONFIG_H */ 345