1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * Configuration settings for the TI OMAP3530 Beagle board. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 #include <asm/sizes.h> 31 32 /* 33 * High Level Configuration Options 34 */ 35 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ 36 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 37 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 38 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 39 #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ 40 41 #include <asm/arch/cpu.h> /* get chip and board defs */ 42 #include <asm/arch/omap3.h> 43 44 /* 45 * Display CPU and Board information 46 */ 47 #define CONFIG_DISPLAY_CPUINFO 1 48 #define CONFIG_DISPLAY_BOARDINFO 1 49 50 /* Clock Defines */ 51 #define V_OSCK 26000000 /* Clock output from T2 */ 52 #define V_SCLK (V_OSCK >> 1) 53 54 #undef CONFIG_USE_IRQ /* no support for IRQs */ 55 #define CONFIG_MISC_INIT_R 56 57 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 58 #define CONFIG_SETUP_MEMORY_TAGS 1 59 #define CONFIG_INITRD_TAG 1 60 #define CONFIG_REVISION_TAG 1 61 62 /* 63 * Size of malloc() pool 64 */ 65 #define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ 66 /* Sector */ 67 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) 68 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 69 /* initial data */ 70 71 /* 72 * Hardware drivers 73 */ 74 75 /* 76 * NS16550 Configuration 77 */ 78 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 79 80 #define CONFIG_SYS_NS16550 81 #define CONFIG_SYS_NS16550_SERIAL 82 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 83 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 84 85 /* 86 * select serial console configuration 87 */ 88 #define CONFIG_CONS_INDEX 3 89 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 90 #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ 91 92 /* allow to overwrite serial and ethaddr */ 93 #define CONFIG_ENV_OVERWRITE 94 #define CONFIG_BAUDRATE 115200 95 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 96 115200} 97 #define CONFIG_MMC 1 98 #define CONFIG_OMAP3_MMC 1 99 #define CONFIG_DOS_PARTITION 1 100 101 /* commands to include */ 102 #include <config_cmd_default.h> 103 104 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 105 #define CONFIG_CMD_FAT /* FAT support */ 106 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 107 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 108 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 109 #define MTDIDS_DEFAULT "nand0=nand" 110 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 111 "1920k(u-boot),128k(u-boot-env),"\ 112 "4m(kernel),-(fs)" 113 114 #define CONFIG_CMD_I2C /* I2C serial bus support */ 115 #define CONFIG_CMD_MMC /* MMC support */ 116 #define CONFIG_CMD_NAND /* NAND support */ 117 118 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 119 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 120 #undef CONFIG_CMD_IMI /* iminfo */ 121 #undef CONFIG_CMD_IMLS /* List all found images */ 122 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 123 #undef CONFIG_CMD_NFS /* NFS support */ 124 125 #define CONFIG_SYS_NO_FLASH 126 #define CONFIG_SYS_I2C_SPEED 100000 127 #define CONFIG_SYS_I2C_SLAVE 1 128 #define CONFIG_SYS_I2C_BUS 0 129 #define CONFIG_SYS_I2C_BUS_SELECT 1 130 #define CONFIG_DRIVER_OMAP34XX_I2C 1 131 132 /* 133 * Board NAND Info. 134 */ 135 #define CONFIG_NAND_OMAP_GPMC 136 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 137 /* to access nand */ 138 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 139 /* to access nand at */ 140 /* CS0 */ 141 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 142 143 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 144 /* devices */ 145 146 #define CONFIG_JFFS2_NAND 147 /* nand device jffs2 lives on */ 148 #define CONFIG_JFFS2_DEV "nand0" 149 /* start of jffs2 partition */ 150 #define CONFIG_JFFS2_PART_OFFSET 0x680000 151 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 152 /* partition */ 153 154 /* Environment information */ 155 #define CONFIG_BOOTDELAY 10 156 157 #define CONFIG_EXTRA_ENV_SETTINGS \ 158 "loadaddr=0x82000000\0" \ 159 "console=ttyS2,115200n8\0" \ 160 "videomode=1024x768@60,vxres=1024,vyres=768\0" \ 161 "videospec=omapfb:vram:2M,vram:4M\0" \ 162 "mmcargs=setenv bootargs console=${console} " \ 163 "video=${videospec},mode:${videomode} " \ 164 "root=/dev/mmcblk0p2 rw " \ 165 "rootfstype=ext3 rootwait\0" \ 166 "nandargs=setenv bootargs console=${console} " \ 167 "video=${videospec},mode:${videomode} " \ 168 "root=/dev/mtdblock4 rw " \ 169 "rootfstype=jffs2\0" \ 170 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 171 "bootscript=echo Running bootscript from mmc ...; " \ 172 "source ${loadaddr}\0" \ 173 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 174 "mmcboot=echo Booting from mmc ...; " \ 175 "run mmcargs; " \ 176 "bootm ${loadaddr}\0" \ 177 "nandboot=echo Booting from nand ...; " \ 178 "run nandargs; " \ 179 "nand read ${loadaddr} 280000 400000; " \ 180 "bootm ${loadaddr}\0" \ 181 182 #define CONFIG_BOOTCOMMAND \ 183 "if mmc init; then " \ 184 "if run loadbootscript; then " \ 185 "run bootscript; " \ 186 "else " \ 187 "if run loaduimage; then " \ 188 "run mmcboot; " \ 189 "else run nandboot; " \ 190 "fi; " \ 191 "fi; " \ 192 "else run nandboot; fi" 193 194 #define CONFIG_AUTO_COMPLETE 1 195 /* 196 * Miscellaneous configurable options 197 */ 198 #define V_PROMPT "OMAP3 beagleboard.org # " 199 200 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 201 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 202 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 203 #define CONFIG_SYS_PROMPT V_PROMPT 204 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 205 /* Print Buffer Size */ 206 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 207 sizeof(CONFIG_SYS_PROMPT) + 16) 208 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 209 /* Boot Argument Buffer Size */ 210 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 211 212 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 213 /* works on */ 214 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 215 0x01F00000) /* 31MB */ 216 217 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 218 /* load address */ 219 220 /* 221 * OMAP3 has 12 GP timers, they can be driven by the system clock 222 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 223 * This rate is divided by a local divisor. 224 */ 225 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 226 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 227 #define CONFIG_SYS_HZ 1000 228 229 /*----------------------------------------------------------------------- 230 * Stack sizes 231 * 232 * The stack sizes are set up in start.S using the settings below 233 */ 234 #define CONFIG_STACKSIZE SZ_128K /* regular stack */ 235 #ifdef CONFIG_USE_IRQ 236 #define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ 237 #define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ 238 #endif 239 240 /*----------------------------------------------------------------------- 241 * Physical Memory Map 242 */ 243 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 244 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 245 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ 246 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 247 248 /* SDRAM Bank Allocation method */ 249 #define SDRC_R_B_C 1 250 251 /*----------------------------------------------------------------------- 252 * FLASH and environment organization 253 */ 254 255 /* **** PISMO SUPPORT *** */ 256 257 /* Configure the PISMO */ 258 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 259 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 260 261 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ 262 /* one chip */ 263 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 264 #define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ 265 266 #define CONFIG_SYS_FLASH_BASE boot_flash_base 267 268 /* Monitor at start of flash */ 269 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 270 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 271 272 #define CONFIG_ENV_IS_IN_NAND 1 273 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 274 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 275 276 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 277 #define CONFIG_ENV_OFFSET boot_flash_off 278 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 279 280 /*----------------------------------------------------------------------- 281 * CFI FLASH driver setup 282 */ 283 /* timeout values are in ticks */ 284 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 285 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 286 287 /* Flash banks JFFS2 should use */ 288 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 289 CONFIG_SYS_MAX_NAND_DEVICE) 290 #define CONFIG_SYS_JFFS2_MEM_NAND 291 /* use flash_info[2] */ 292 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 293 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 294 295 #ifndef __ASSEMBLY__ 296 extern gpmc_csx_t *nand_cs_base; 297 extern gpmc_t *gpmc_cfg_base; 298 extern unsigned int boot_flash_base; 299 extern volatile unsigned int boot_flash_env_addr; 300 extern unsigned int boot_flash_off; 301 extern unsigned int boot_flash_sec; 302 extern unsigned int boot_flash_type; 303 #endif 304 305 #endif /* __CONFIG_H */ 306