1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 4 * 5 * Configuration settings for the Boundary Devices Nitrogen6X 6 * and Freescale i.MX6Q Sabre Lite boards. 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "mx6_common.h" 13 14 #define CONFIG_MACH_TYPE 3769 15 16 /* Size of malloc() pool */ 17 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 18 19 #define CONFIG_USBD_HS 20 #define CONFIG_NETCONSOLE 21 22 #define CONFIG_MXC_UART 23 #define CONFIG_MXC_UART_BASE UART2_BASE 24 25 #ifdef CONFIG_CMD_SF 26 #define CONFIG_SF_DEFAULT_BUS 0 27 #define CONFIG_SF_DEFAULT_CS 0 28 #define CONFIG_SF_DEFAULT_SPEED 25000000 29 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 30 #endif 31 32 /* I2C Configs */ 33 #define CONFIG_SYS_I2C 34 #define CONFIG_SYS_I2C_MXC 35 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 36 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 37 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 38 #define CONFIG_SYS_I2C_SPEED 100000 39 #define CONFIG_I2C_EDID 40 41 /* MMC Configs */ 42 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 43 #define CONFIG_SYS_FSL_USDHC_NUM 2 44 45 /* 46 * SATA Configs 47 */ 48 #ifdef CONFIG_CMD_SATA 49 #define CONFIG_SYS_SATA_MAX_DEVICE 1 50 #define CONFIG_DWC_AHSATA_PORT_ID 0 51 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 52 #define CONFIG_LBA48 53 #endif 54 55 #define CONFIG_FEC_MXC 56 #define IMX_FEC_BASE ENET_BASE_ADDR 57 #define CONFIG_FEC_XCV_TYPE RGMII 58 #define CONFIG_ETHPRIME "FEC" 59 #define CONFIG_FEC_MXC_PHYADDR 6 60 61 /* USB Configs */ 62 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 63 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 64 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 65 #define CONFIG_MXC_USB_FLAGS 0 66 67 /* Framebuffer and LCD */ 68 #define CONFIG_VIDEO_IPUV3 69 #define CONFIG_VIDEO_BMP_RLE8 70 #define CONFIG_SPLASH_SCREEN 71 #define CONFIG_SPLASH_SCREEN_ALIGN 72 #define CONFIG_VIDEO_BMP_GZIP 73 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024) 74 #define CONFIG_BMP_16BPP 75 #define CONFIG_IMX_HDMI 76 #define CONFIG_IMX_VIDEO_SKIP 77 78 #define CONFIG_PREBOOT "" 79 80 #ifdef CONFIG_CMD_MMC 81 #define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) 82 #else 83 #define DISTRO_BOOT_DEV_MMC(func) 84 #endif 85 86 #ifdef CONFIG_CMD_SATA 87 #define DISTRO_BOOT_DEV_SATA(func) func(SATA, sata, 0) 88 #else 89 #define DISTRO_BOOT_DEV_SATA(func) 90 #endif 91 92 #ifdef CONFIG_USB_STORAGE 93 #define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0) 94 #else 95 #define DISTRO_BOOT_DEV_USB(func) 96 #endif 97 98 #ifdef CONFIG_CMD_PXE 99 #define DISTRO_BOOT_DEV_PXE(func) func(PXE, pxe, na) 100 #else 101 #define DISTRO_BOOT_DEV_PXE(func) 102 #endif 103 104 #ifdef CONFIG_CMD_DHCP 105 #define DISTRO_BOOT_DEV_DHCP(func) func(DHCP, dhcp, na) 106 #else 107 #define DISTRO_BOOT_DEV_DHCP(func) 108 #endif 109 110 111 #if defined(CONFIG_SABRELITE) 112 #define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0" 113 #else 114 /* FIXME: nitrogen6x covers multiple configs. Define fdtfile for each supported config. */ 115 #define FDTFILE 116 #endif 117 118 #define BOOT_TARGET_DEVICES(func) \ 119 DISTRO_BOOT_DEV_MMC(func) \ 120 DISTRO_BOOT_DEV_SATA(func) \ 121 DISTRO_BOOT_DEV_USB(func) \ 122 DISTRO_BOOT_DEV_PXE(func) \ 123 DISTRO_BOOT_DEV_DHCP(func) 124 125 #include <config_distro_bootcmd.h> 126 127 #define CONFIG_EXTRA_ENV_SETTINGS \ 128 "console=ttymxc1\0" \ 129 "fdt_high=0xffffffff\0" \ 130 "initrd_high=0xffffffff\0" \ 131 "fdt_addr_r=0x18000000\0" \ 132 FDTFILE \ 133 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ 134 "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ 135 "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ 136 "ramdisk_addr_r=0x13000000\0" \ 137 "ramdiskaddr=0x13000000\0" \ 138 "ip_dyn=yes\0" \ 139 "usb_pgood_delay=2000\0" \ 140 BOOTENV 141 142 /* Miscellaneous configurable options */ 143 #define CONFIG_SYS_MEMTEST_START 0x10000000 144 #define CONFIG_SYS_MEMTEST_END 0x10010000 145 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 146 147 /* Physical Memory Map */ 148 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 149 150 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 151 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 152 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 153 154 #define CONFIG_SYS_INIT_SP_OFFSET \ 155 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 156 #define CONFIG_SYS_INIT_SP_ADDR \ 157 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 158 159 /* Environment organization */ 160 #define CONFIG_ENV_SIZE (8 * 1024) 161 162 #if defined(CONFIG_ENV_IS_IN_MMC) 163 #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 164 #define CONFIG_SYS_MMC_ENV_DEV 0 165 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) 166 #define CONFIG_ENV_OFFSET (768 * 1024) 167 #define CONFIG_ENV_SECT_SIZE (8 * 1024) 168 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 169 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 170 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 171 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 172 #endif 173 174 /* 175 * PCI express 176 */ 177 #ifdef CONFIG_CMD_PCI 178 #define CONFIG_PCI_SCAN_SHOW 179 #define CONFIG_PCIE_IMX 180 #endif 181 182 #endif /* __CONFIG_H */ 183