xref: /openbmc/u-boot/include/configs/nitrogen6x.h (revision 5053b593)
1 /*
2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * Configuration settings for the Boundary Devices Nitrogen6X
5  * and Freescale i.MX6Q Sabre Lite boards.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.		See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #ifndef __CONFIG_H
24 #define __CONFIG_H
25 
26 #define CONFIG_MX6
27 #define CONFIG_DISPLAY_CPUINFO
28 #define CONFIG_DISPLAY_BOARDINFO
29 
30 #define CONFIG_MACH_TYPE	3769
31 
32 #include <asm/arch/imx-regs.h>
33 #include <asm/imx-common/gpio.h>
34 
35 #define CONFIG_CMDLINE_TAG
36 #define CONFIG_SETUP_MEMORY_TAGS
37 #define CONFIG_INITRD_TAG
38 #define CONFIG_REVISION_TAG
39 
40 /* Size of malloc() pool */
41 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
42 
43 #define CONFIG_BOARD_EARLY_INIT_F
44 #define CONFIG_MISC_INIT_R
45 #define CONFIG_MXC_GPIO
46 
47 #define CONFIG_CMD_FUSE
48 #ifdef CONFIG_CMD_FUSE
49 #define CONFIG_MXC_OCOTP
50 #endif
51 
52 #define CONFIG_MXC_UART
53 #define CONFIG_MXC_UART_BASE	       UART2_BASE
54 
55 #define CONFIG_CMD_SF
56 #ifdef CONFIG_CMD_SF
57 #define CONFIG_SPI_FLASH
58 #define CONFIG_SPI_FLASH_SST
59 #define CONFIG_MXC_SPI
60 #define CONFIG_SF_DEFAULT_BUS  0
61 #define CONFIG_SF_DEFAULT_CS   (0|(IMX_GPIO_NR(3, 19)<<8))
62 #define CONFIG_SF_DEFAULT_SPEED 25000000
63 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
64 #endif
65 
66 /* I2C Configs */
67 #define CONFIG_CMD_I2C
68 #define CONFIG_I2C_MULTI_BUS
69 #define CONFIG_I2C_MXC
70 #define CONFIG_SYS_I2C_SPEED		100000
71 
72 /* OCOTP Configs */
73 #define CONFIG_CMD_IMXOTP
74 #ifdef CONFIG_CMD_IMXOTP
75 #define CONFIG_IMX_OTP
76 #define IMX_OTP_BASE			OCOTP_BASE_ADDR
77 #define IMX_OTP_ADDR_MAX		0x7F
78 #define IMX_OTP_DATA_ERROR_VAL		0xBADABADA
79 #define IMX_OTPWRITE_ENABLED
80 #endif
81 
82 /* MMC Configs */
83 #define CONFIG_FSL_ESDHC
84 #define CONFIG_FSL_USDHC
85 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
86 #define CONFIG_SYS_FSL_USDHC_NUM       2
87 
88 #define CONFIG_MMC
89 #define CONFIG_CMD_MMC
90 #define CONFIG_GENERIC_MMC
91 #define CONFIG_BOUNCE_BUFFER
92 #define CONFIG_CMD_EXT2
93 #define CONFIG_CMD_FAT
94 #define CONFIG_DOS_PARTITION
95 
96 #ifdef CONFIG_MX6Q
97 #define CONFIG_CMD_SATA
98 #endif
99 
100 /*
101  * SATA Configs
102  */
103 #ifdef CONFIG_CMD_SATA
104 #define CONFIG_DWC_AHSATA
105 #define CONFIG_SYS_SATA_MAX_DEVICE	1
106 #define CONFIG_DWC_AHSATA_PORT_ID	0
107 #define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
108 #define CONFIG_LBA48
109 #define CONFIG_LIBATA
110 #endif
111 
112 #define CONFIG_CMD_PING
113 #define CONFIG_CMD_DHCP
114 #define CONFIG_CMD_MII
115 #define CONFIG_CMD_NET
116 #define CONFIG_FEC_MXC
117 #define CONFIG_MII
118 #define IMX_FEC_BASE			ENET_BASE_ADDR
119 #define CONFIG_FEC_XCV_TYPE		RGMII
120 #define CONFIG_ETHPRIME			"FEC"
121 #define CONFIG_FEC_MXC_PHYADDR		6
122 #define CONFIG_PHYLIB
123 #define CONFIG_PHY_MICREL
124 #define CONFIG_PHY_MICREL_KSZ9021
125 
126 /* USB Configs */
127 #define CONFIG_CMD_USB
128 #define CONFIG_CMD_FAT
129 #define CONFIG_USB_EHCI
130 #define CONFIG_USB_EHCI_MX6
131 #define CONFIG_USB_STORAGE
132 #define CONFIG_USB_HOST_ETHER
133 #define CONFIG_USB_ETHER_ASIX
134 #define CONFIG_USB_ETHER_SMSC95XX
135 #define CONFIG_MXC_USB_PORT	1
136 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
137 #define CONFIG_MXC_USB_FLAGS	0
138 
139 /* Miscellaneous commands */
140 #define CONFIG_CMD_BMODE
141 #define CONFIG_CMD_SETEXPR
142 
143 /* Framebuffer and LCD */
144 #define CONFIG_VIDEO
145 #define CONFIG_VIDEO_IPUV3
146 #define CONFIG_CFB_CONSOLE
147 #define CONFIG_VGA_AS_SINGLE_DEVICE
148 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
149 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
150 #define CONFIG_VIDEO_BMP_RLE8
151 #define CONFIG_SPLASH_SCREEN
152 #define CONFIG_BMP_16BPP
153 #define CONFIG_VIDEO_LOGO
154 #define CONFIG_IPUV3_CLK 260000000
155 #define CONFIG_CMD_HDMIDETECT
156 #define CONFIG_CONSOLE_MUX
157 
158 /* allow to overwrite serial and ethaddr */
159 #define CONFIG_ENV_OVERWRITE
160 #define CONFIG_CONS_INDEX	       1
161 #define CONFIG_BAUDRATE			       115200
162 
163 /* Command definition */
164 #include <config_cmd_default.h>
165 
166 #undef CONFIG_CMD_IMLS
167 
168 #define CONFIG_BOOTDELAY	       1
169 
170 #define CONFIG_PREBOOT                 ""
171 
172 #define CONFIG_LOADADDR			       0x12000000
173 #define CONFIG_SYS_TEXT_BASE	       0x17800000
174 
175 #ifdef CONFIG_CMD_SATA
176 #define CONFIG_DRIVE_SATA "sata "
177 #else
178 #define CONFIG_DRIVE_SATA
179 #endif
180 
181 #ifdef CONFIG_CMD_MMC
182 #define CONFIG_DRIVE_MMC "mmc "
183 #else
184 #define CONFIG_DRIVE_MMC
185 #endif
186 
187 #define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
188 
189 #define CONFIG_EXTRA_ENV_SETTINGS \
190 	"console=ttymxc1\0" \
191 	"clearenv=if sf probe || sf probe || sf probe 1 ; then " \
192 		"sf erase 0xc0000 0x2000 && " \
193 		"echo restored environment to factory default ; fi\0" \
194 	"bootcmd=for dtype in " CONFIG_DRIVE_TYPES \
195 		"; do " \
196 			"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
197 				"for fs in fat ext2 ; do " \
198 					"${fs}load " \
199 						"${dtype} ${disk}:1 " \
200 						"10008000 " \
201 						"/6x_bootscript" \
202 						"&& source 10008000 ; " \
203 				"done ; " \
204 			"done ; " \
205 		"done; " \
206 		"setenv stdout serial,vga ; " \
207 		"echo ; echo 6x_bootscript not found ; " \
208 		"echo ; echo serial console at 115200, 8N1 ; echo ; " \
209 		"echo details at http://boundarydevices.com/6q_bootscript ; " \
210 		"setenv stdout serial\0" \
211 	"upgradeu=for dtype in " CONFIG_DRIVE_TYPES \
212 		"; do " \
213 		"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
214 		     "for fs in fat ext2 ; do " \
215 				"${fs}load ${dtype} ${disk}:1 10008000 " \
216 					"/6x_upgrade " \
217 					"&& source 10008000 ; " \
218 			"done ; " \
219 		"done ; " \
220 	"done\0" \
221 
222 /* Miscellaneous configurable options */
223 #define CONFIG_SYS_LONGHELP
224 #define CONFIG_SYS_HUSH_PARSER
225 #define CONFIG_SYS_PROMPT	       "U-Boot > "
226 #define CONFIG_AUTO_COMPLETE
227 #define CONFIG_SYS_CBSIZE	       1024
228 
229 /* Print Buffer Size */
230 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
231 #define CONFIG_SYS_MAXARGS	       16
232 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
233 
234 #define CONFIG_SYS_MEMTEST_START       0x10000000
235 #define CONFIG_SYS_MEMTEST_END	       0x10010000
236 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
237 
238 #define CONFIG_SYS_LOAD_ADDR	       CONFIG_LOADADDR
239 #define CONFIG_SYS_HZ		       1000
240 
241 #define CONFIG_CMDLINE_EDITING
242 
243 /* Physical Memory Map */
244 #define CONFIG_NR_DRAM_BANKS	       1
245 #define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
246 
247 #define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
248 #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
249 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
250 
251 #define CONFIG_SYS_INIT_SP_OFFSET \
252 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
253 #define CONFIG_SYS_INIT_SP_ADDR \
254 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
255 
256 /* FLASH and environment organization */
257 #define CONFIG_SYS_NO_FLASH
258 
259 #define CONFIG_ENV_SIZE			(8 * 1024)
260 
261 /* #define CONFIG_ENV_IS_IN_MMC */
262 #define CONFIG_ENV_IS_IN_SPI_FLASH
263 
264 #if defined(CONFIG_ENV_IS_IN_MMC)
265 #define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
266 #define CONFIG_SYS_MMC_ENV_DEV		0
267 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
268 #define CONFIG_ENV_OFFSET		(768 * 1024)
269 #define CONFIG_ENV_SECT_SIZE		(8 * 1024)
270 #define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
271 #define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
272 #define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
273 #define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
274 #endif
275 
276 #define CONFIG_OF_LIBFDT
277 #define CONFIG_CMD_BOOTZ
278 
279 #define CONFIG_SYS_DCACHE_OFF
280 
281 #ifndef CONFIG_SYS_DCACHE_OFF
282 #define CONFIG_CMD_CACHE
283 #endif
284 
285 #define CONFIG_CMD_BMP
286 
287 #define CONFIG_CMD_TIME
288 #define CONFIG_SYS_ALT_MEMTEST
289 
290 #endif	       /* __CONFIG_H */
291