1 /* 2 * Copyright (C) 2013 Marek Vasut <marex@denx.de> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 #ifndef __CONFIGS_MXS_H__ 20 #define __CONFIGS_MXS_H__ 21 22 /* 23 * Includes 24 */ 25 26 #if defined(CONFIG_MX23) && defined(CONFIG_MX28) 27 #error Select either CONFIG_MX23 or CONFIG_MX28 , never both! 28 #elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28) 29 #error Select one of CONFIG_MX23 or CONFIG_MX28 ! 30 #endif 31 32 #include <asm/arch/regs-base.h> 33 34 #if defined(CONFIG_MX23) 35 #include <asm/arch/iomux-mx23.h> 36 #elif defined(CONFIG_MX28) 37 #include <asm/arch/iomux-mx28.h> 38 #endif 39 40 /* 41 * CPU specifics 42 */ 43 44 /* Startup hooks */ 45 46 /* SPL */ 47 #define CONFIG_SPL_NO_CPU_SUPPORT_CODE 48 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" 49 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" 50 51 /* Memory sizes */ 52 #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ 53 #define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ 54 #define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ 55 56 /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ 57 #define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 58 #if defined(CONFIG_MX23) 59 #define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024) 60 #elif defined(CONFIG_MX28) 61 #define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) 62 #endif 63 64 /* Point initial SP in SRAM so SPL can use it too. */ 65 #define CONFIG_SYS_INIT_SP_OFFSET \ 66 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 67 #define CONFIG_SYS_INIT_SP_ADDR \ 68 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 69 70 /* 71 * We need to sacrifice first 4 bytes of RAM here to avoid triggering some 72 * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot 73 * binary. In case there was more of this mess, 0x100 bytes are skipped. 74 * 75 * In case of a HAB boot, we cannot for some weird reason use the first 4KiB 76 * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST 77 * blocks, thus U-Boot starts at offset +8 KiB of DRAM start. 78 * 79 * As for the SPL, we must avoid the first 4 KiB as well, but we load the 80 * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB. 81 */ 82 #define CONFIG_SYS_TEXT_BASE 0x40002000 83 #define CONFIG_SPL_TEXT_BASE 0x00001000 84 85 /* U-Boot general configuration */ 86 #define CONFIG_SYS_LONGHELP 87 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 88 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 89 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 90 /* Boot argument buffer size */ 91 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 92 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 93 94 /* Booting Linux */ 95 #define CONFIG_CMDLINE_TAG 96 #define CONFIG_SETUP_MEMORY_TAGS 97 98 /* 99 * Drivers 100 */ 101 102 /* APBH DMA */ 103 #define CONFIG_APBH_DMA 104 105 /* GPIO */ 106 #define CONFIG_MXS_GPIO 107 108 /* 109 * DUART Serial Driver. 110 * Conflicts with AUART driver which can be set by board. 111 */ 112 #define CONFIG_PL011_SERIAL 113 #define CONFIG_PL011_CLOCK 24000000 114 #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } 115 #define CONFIG_CONS_INDEX 0 116 /* Default baudrate can be overridden by board! */ 117 118 /* FEC Ethernet on SoC */ 119 #ifdef CONFIG_FEC_MXC 120 #define CONFIG_MII 121 #ifndef CONFIG_ETHPRIME 122 #define CONFIG_ETHPRIME "FEC0" 123 #endif 124 #ifndef CONFIG_FEC_XCV_TYPE 125 #define CONFIG_FEC_XCV_TYPE RMII 126 #endif 127 #endif 128 129 /* I2C */ 130 #ifdef CONFIG_CMD_I2C 131 #define CONFIG_SYS_I2C 132 #define CONFIG_SYS_I2C_MXS 133 #define CONFIG_HARD_I2C 134 #ifndef CONFIG_SYS_I2C_SPEED 135 #define CONFIG_SYS_I2C_SPEED 400000 136 #endif 137 #endif 138 139 /* LCD */ 140 #ifdef CONFIG_VIDEO 141 #define CONFIG_VIDEO_MXS 142 #endif 143 144 /* MMC */ 145 #ifdef CONFIG_CMD_MMC 146 #define CONFIG_BOUNCE_BUFFER 147 #endif 148 149 /* NAND */ 150 #ifdef CONFIG_CMD_NAND 151 #define CONFIG_NAND_MXS 152 #define CONFIG_SYS_MAX_NAND_DEVICE 1 153 #define CONFIG_SYS_NAND_BASE 0x60000000 154 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 155 #endif 156 157 /* OCOTP */ 158 #ifdef CONFIG_CMD_FUSE 159 #define CONFIG_MXS_OCOTP 160 #endif 161 162 /* SPI */ 163 #ifdef CONFIG_CMD_SPI 164 #define CONFIG_HARD_SPI 165 #define CONFIG_MXS_SPI 166 #define CONFIG_SPI_HALF_DUPLEX 167 #endif 168 169 /* USB */ 170 #ifdef CONFIG_CMD_USB 171 #define CONFIG_USB_EHCI 172 #define CONFIG_USB_EHCI_MXS 173 #define CONFIG_EHCI_IS_TDI 174 #endif 175 176 #endif /* __CONFIGS_MXS_H__ */ 177