1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the Freescale i.MX7D SABRESD board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __MX7D_SABRESD_CONFIG_H 10 #define __MX7D_SABRESD_CONFIG_H 11 12 #include "mx7_common.h" 13 14 #define CONFIG_DBG_MONITOR 15 #define PHYS_SDRAM_SIZE SZ_1G 16 17 #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR 18 19 /* Size of malloc() pool */ 20 #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) 21 22 #define CONFIG_BOARD_EARLY_INIT_F 23 #define CONFIG_BOARD_LATE_INIT 24 25 /* Uncomment to enable secure boot support */ 26 /* #define CONFIG_SECURE_BOOT */ 27 #define CONFIG_CSF_SIZE 0x4000 28 29 /* Network */ 30 #define CONFIG_FEC_MXC 31 #define CONFIG_MII 32 #define CONFIG_FEC_XCV_TYPE RGMII 33 #define CONFIG_ETHPRIME "FEC" 34 #define CONFIG_FEC_MXC_PHYADDR 0 35 36 #define CONFIG_PHYLIB 37 #define CONFIG_PHY_BROADCOM 38 /* ENET1 */ 39 #define IMX_FEC_BASE ENET_IPS_BASE_ADDR 40 41 /* MMC Config*/ 42 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 43 44 /* PMIC */ 45 #define CONFIG_POWER 46 #define CONFIG_POWER_I2C 47 #define CONFIG_POWER_PFUZE3000 48 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 49 50 #undef CONFIG_BOOTM_NETBSD 51 #undef CONFIG_BOOTM_PLAN9 52 #undef CONFIG_BOOTM_RTEMS 53 54 /* I2C configs */ 55 #define CONFIG_SYS_I2C 56 #define CONFIG_SYS_I2C_MXC 57 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 58 #define CONFIG_SYS_I2C_SPEED 100000 59 60 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ 61 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 62 63 #ifdef CONFIG_IMX_BOOTAUX 64 /* Set to QSPI1 A flash at default */ 65 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000 66 67 #define UPDATE_M4_ENV \ 68 "m4image=m4_qspi.bin\0" \ 69 "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ 70 "update_m4_from_sd=" \ 71 "if sf probe 0:0; then " \ 72 "if run loadm4image; then " \ 73 "setexpr fw_sz ${filesize} + 0xffff; " \ 74 "setexpr fw_sz ${fw_sz} / 0x10000; " \ 75 "setexpr fw_sz ${fw_sz} * 0x10000; " \ 76 "sf erase 0x0 ${fw_sz}; " \ 77 "sf write ${loadaddr} 0x0 ${filesize}; " \ 78 "fi; " \ 79 "fi\0" \ 80 "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" 81 #else 82 #define UPDATE_M4_ENV "" 83 #endif 84 85 #define CONFIG_MFG_ENV_SETTINGS \ 86 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ 87 "rdinit=/linuxrc " \ 88 "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ 89 "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ 90 "g_mass_storage.iSerialNumber=\"\" "\ 91 "clk_ignore_unused "\ 92 "\0" \ 93 "initrd_addr=0x83800000\0" \ 94 "initrd_high=0xffffffff\0" \ 95 "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ 96 97 #define CONFIG_DFU_ENV_SETTINGS \ 98 "dfu_alt_info=image raw 0 0x800000;"\ 99 "u-boot raw 0 0x4000;"\ 100 "bootimg part 0 1;"\ 101 "rootfs part 0 2\0" \ 102 103 #define CONFIG_EXTRA_ENV_SETTINGS \ 104 UPDATE_M4_ENV \ 105 CONFIG_MFG_ENV_SETTINGS \ 106 CONFIG_DFU_ENV_SETTINGS \ 107 "script=boot.scr\0" \ 108 "image=zImage\0" \ 109 "console=ttymxc0\0" \ 110 "fdt_high=0xffffffff\0" \ 111 "initrd_high=0xffffffff\0" \ 112 "fdt_file=imx7d-sdb.dtb\0" \ 113 "fdt_addr=0x83000000\0" \ 114 "boot_fdt=try\0" \ 115 "ip_dyn=yes\0" \ 116 "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ 117 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ 118 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 119 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 120 "mmcautodetect=yes\0" \ 121 "mmcargs=setenv bootargs console=${console},${baudrate} " \ 122 "root=${mmcroot}\0" \ 123 "loadbootscript=" \ 124 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 125 "bootscript=echo Running bootscript from mmc ...; " \ 126 "source\0" \ 127 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 128 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 129 "mmcboot=echo Booting from mmc ...; " \ 130 "run mmcargs; " \ 131 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 132 "if run loadfdt; then " \ 133 "bootz ${loadaddr} - ${fdt_addr}; " \ 134 "else " \ 135 "if test ${boot_fdt} = try; then " \ 136 "bootz; " \ 137 "else " \ 138 "echo WARN: Cannot load the DT; " \ 139 "fi; " \ 140 "fi; " \ 141 "else " \ 142 "bootz; " \ 143 "fi;\0" \ 144 "netargs=setenv bootargs console=${console},${baudrate} " \ 145 "root=/dev/nfs " \ 146 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 147 "netboot=echo Booting from net ...; " \ 148 "run netargs; " \ 149 "if test ${ip_dyn} = yes; then " \ 150 "setenv get_cmd dhcp; " \ 151 "else " \ 152 "setenv get_cmd tftp; " \ 153 "fi; " \ 154 "${get_cmd} ${image}; " \ 155 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 156 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 157 "bootz ${loadaddr} - ${fdt_addr}; " \ 158 "else " \ 159 "if test ${boot_fdt} = try; then " \ 160 "bootz; " \ 161 "else " \ 162 "echo WARN: Cannot load the DT; " \ 163 "fi; " \ 164 "fi; " \ 165 "else " \ 166 "bootz; " \ 167 "fi;\0" 168 169 #define CONFIG_BOOTCOMMAND \ 170 "mmc dev ${mmcdev};" \ 171 "mmc dev ${mmcdev}; if mmc rescan; then " \ 172 "if run loadbootscript; then " \ 173 "run bootscript; " \ 174 "else " \ 175 "if run loadimage; then " \ 176 "run mmcboot; " \ 177 "else run netboot; " \ 178 "fi; " \ 179 "fi; " \ 180 "else run netboot; fi" 181 182 #define CONFIG_SYS_MEMTEST_START 0x80000000 183 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) 184 185 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 186 #define CONFIG_SYS_HZ 1000 187 188 #define CONFIG_STACKSIZE SZ_128K 189 190 /* Physical Memory Map */ 191 #define CONFIG_NR_DRAM_BANKS 1 192 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 193 194 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 195 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 196 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 197 198 #define CONFIG_SYS_INIT_SP_OFFSET \ 199 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 200 #define CONFIG_SYS_INIT_SP_ADDR \ 201 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 202 203 /* FLASH and environment organization */ 204 #define CONFIG_SYS_NO_FLASH 205 #define CONFIG_ENV_SIZE SZ_8K 206 #define CONFIG_ENV_IS_IN_MMC 207 208 /* 209 * If want to use nand, define CONFIG_NAND_MXS and rework board 210 * to support nand, since emmc has pin conflicts with nand 211 */ 212 #ifdef CONFIG_NAND_MXS 213 #define CONFIG_CMD_NAND 214 #define CONFIG_CMD_NAND_TRIMFFS 215 216 /* NAND stuff */ 217 #define CONFIG_SYS_MAX_NAND_DEVICE 1 218 #define CONFIG_SYS_NAND_BASE 0x40000000 219 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 220 #define CONFIG_SYS_NAND_ONFI_DETECTION 221 222 /* DMA stuff, needed for GPMI/MXS NAND support */ 223 #define CONFIG_APBH_DMA 224 #define CONFIG_APBH_DMA_BURST 225 #define CONFIG_APBH_DMA_BURST8 226 #endif 227 228 #define CONFIG_ENV_OFFSET (8 * SZ_64K) 229 #ifdef CONFIG_NAND_MXS 230 #define CONFIG_SYS_FSL_USDHC_NUM 1 231 #else 232 #define CONFIG_SYS_FSL_USDHC_NUM 2 233 #endif 234 235 #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ 236 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ 237 #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ 238 239 /* USB Configs */ 240 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 241 #define CONFIG_USB_HOST_ETHER 242 #define CONFIG_USB_ETHER_ASIX 243 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 244 #define CONFIG_MXC_USB_FLAGS 0 245 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 246 247 #define CONFIG_IMX_THERMAL 248 249 #define CONFIG_USBD_HS 250 251 #define CONFIG_USB_FUNCTION_MASS_STORAGE 252 253 #define CONFIG_VIDEO 254 #ifdef CONFIG_VIDEO 255 #define CONFIG_CFB_CONSOLE 256 #define CONFIG_VIDEO_MXS 257 #define CONFIG_VIDEO_LOGO 258 #define CONFIG_VIDEO_SW_CURSOR 259 #define CONFIG_VGA_AS_SINGLE_DEVICE 260 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 261 #define CONFIG_SPLASH_SCREEN 262 #define CONFIG_SPLASH_SCREEN_ALIGN 263 #define CONFIG_CMD_BMP 264 #define CONFIG_BMP_16BPP 265 #define CONFIG_VIDEO_BMP_RLE8 266 #define CONFIG_VIDEO_BMP_LOGO 267 #endif 268 269 #ifdef CONFIG_FSL_QSPI 270 #define CONFIG_SPI_FLASH 271 #define CONFIG_SPI_FLASH_MACRONIX 272 #define CONFIG_SPI_FLASH_BAR 273 #define CONFIG_SF_DEFAULT_BUS 0 274 #define CONFIG_SF_DEFAULT_CS 0 275 #define CONFIG_SF_DEFAULT_SPEED 40000000 276 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 277 #define FSL_QSPI_FLASH_NUM 1 278 #define FSL_QSPI_FLASH_SIZE SZ_64M 279 #define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR 280 #define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR 281 #endif 282 283 #endif /* __CONFIG_H */ 284