xref: /openbmc/u-boot/include/configs/mx6ullevk.h (revision dd1033e4)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2016 Freescale Semiconductor, Inc.
4  *
5  * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
6  */
7 #ifndef __MX6ULLEVK_CONFIG_H
8 #define __MX6ULLEVK_CONFIG_H
9 
10 
11 #include <asm/arch/imx-regs.h>
12 #include <linux/sizes.h>
13 #include "mx6_common.h"
14 #include <asm/mach-imx/gpio.h>
15 
16 #ifdef CONFIG_SECURE_BOOT
17 #ifndef CONFIG_CSF_SIZE
18 #define CONFIG_CSF_SIZE 0x4000
19 #endif
20 #endif
21 
22 #define PHYS_SDRAM_SIZE	SZ_512M
23 
24 /* Size of malloc() pool */
25 #define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
26 
27 #define CONFIG_MXC_UART
28 #define CONFIG_MXC_UART_BASE		UART1_BASE
29 
30 /* MMC Configs */
31 #ifdef CONFIG_FSL_USDHC
32 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
33 
34 /* NAND pin conflicts with usdhc2 */
35 #ifdef CONFIG_SYS_USE_NAND
36 #define CONFIG_SYS_FSL_USDHC_NUM	1
37 #else
38 #define CONFIG_SYS_FSL_USDHC_NUM	2
39 #endif
40 #endif
41 
42 /* I2C configs */
43 #ifdef CONFIG_CMD_I2C
44 #define CONFIG_SYS_I2C_MXC
45 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
46 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
47 #define CONFIG_SYS_I2C_SPEED		100000
48 #endif
49 
50 #define CONFIG_SYS_MMC_IMG_LOAD_PART	1
51 
52 #define CONFIG_EXTRA_ENV_SETTINGS \
53 	"script=boot.scr\0" \
54 	"image=zImage\0" \
55 	"console=ttymxc0\0" \
56 	"fdt_high=0xffffffff\0" \
57 	"initrd_high=0xffffffff\0" \
58 	"fdt_file=imx6ull-14x14-evk.dtb\0" \
59 	"fdt_addr=0x83000000\0" \
60 	"boot_fdt=try\0" \
61 	"ip_dyn=yes\0" \
62 	"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
63 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
64 	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
65 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
66 	"mmcautodetect=yes\0" \
67 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
68 		"root=${mmcroot}\0" \
69 	"loadbootscript=" \
70 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
71 	"bootscript=echo Running bootscript from mmc ...; " \
72 		"source\0" \
73 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
74 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
75 	"mmcboot=echo Booting from mmc ...; " \
76 		"run mmcargs; " \
77 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
78 			"if run loadfdt; then " \
79 				"bootz ${loadaddr} - ${fdt_addr}; " \
80 			"else " \
81 				"if test ${boot_fdt} = try; then " \
82 					"bootz; " \
83 				"else " \
84 					"echo WARN: Cannot load the DT; " \
85 				"fi; " \
86 			"fi; " \
87 		"else " \
88 			"bootz; " \
89 		"fi;\0" \
90 	"netargs=setenv bootargs console=${console},${baudrate} " \
91 		"root=/dev/nfs " \
92 	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
93 		"netboot=echo Booting from net ...; " \
94 		"run netargs; " \
95 		"if test ${ip_dyn} = yes; then " \
96 			"setenv get_cmd dhcp; " \
97 		"else " \
98 			"setenv get_cmd tftp; " \
99 		"fi; " \
100 		"${get_cmd} ${image}; " \
101 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
102 			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
103 				"bootz ${loadaddr} - ${fdt_addr}; " \
104 			"else " \
105 				"if test ${boot_fdt} = try; then " \
106 					"bootz; " \
107 				"else " \
108 					"echo WARN: Cannot load the DT; " \
109 				"fi; " \
110 			"fi; " \
111 		"else " \
112 			"bootz; " \
113 		"fi;\0" \
114 
115 #define CONFIG_BOOTCOMMAND \
116 	   "mmc dev ${mmcdev};" \
117 	   "mmc dev ${mmcdev}; if mmc rescan; then " \
118 		   "if run loadbootscript; then " \
119 			   "run bootscript; " \
120 		   "else " \
121 			   "if run loadimage; then " \
122 				   "run mmcboot; " \
123 			   "else run netboot; " \
124 			   "fi; " \
125 		   "fi; " \
126 	   "else run netboot; fi"
127 
128 /* Miscellaneous configurable options */
129 #define CONFIG_SYS_MEMTEST_START	0x80000000
130 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x8000000)
131 
132 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
133 #define CONFIG_SYS_HZ			1000
134 
135 /* Physical Memory Map */
136 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
137 
138 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
139 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
140 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
141 
142 #define CONFIG_SYS_INIT_SP_OFFSET \
143 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
144 #define CONFIG_SYS_INIT_SP_ADDR \
145 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
146 
147 /* environment organization */
148 #define CONFIG_SYS_MMC_ENV_DEV		1	/* USDHC2 */
149 #define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
150 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
151 
152 #define CONFIG_ENV_SIZE			SZ_8K
153 #define CONFIG_ENV_OFFSET		(12 * SZ_64K)
154 
155 #define CONFIG_IMX_THERMAL
156 
157 #define CONFIG_IOMUX_LPSR
158 
159 #define CONFIG_SOFT_SPI
160 
161 #ifdef CONFIG_FSL_QSPI
162 #define CONFIG_SYS_FSL_QSPI_AHB
163 #define CONFIG_SF_DEFAULT_BUS		0
164 #define CONFIG_SF_DEFAULT_CS		0
165 #define CONFIG_SF_DEFAULT_SPEED	40000000
166 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
167 #define FSL_QSPI_FLASH_NUM		1
168 #define FSL_QSPI_FLASH_SIZE		SZ_32M
169 #endif
170 
171 #endif
172