1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the Freescale i.MX6SX Sabresd board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "mx6_common.h" 14 15 #ifdef CONFIG_SPL 16 #define CONFIG_SPL_LIBCOMMON_SUPPORT 17 #define CONFIG_SPL_MMC_SUPPORT 18 #include "imx6_spl.h" 19 #endif 20 21 /* Size of malloc() pool */ 22 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) 23 24 #define CONFIG_BOARD_EARLY_INIT_F 25 26 #define CONFIG_MXC_UART 27 #define CONFIG_MXC_UART_BASE UART1_BASE 28 29 #ifdef CONFIG_IMX_BOOTAUX 30 /* Set to QSPI2 B flash at default */ 31 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 32 #define CONFIG_CMD_SETEXPR 33 34 #define UPDATE_M4_ENV \ 35 "m4image=m4_qspi.bin\0" \ 36 "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ 37 "update_m4_from_sd=" \ 38 "if sf probe 1:0; then " \ 39 "if run loadm4image; then " \ 40 "setexpr fw_sz ${filesize} + 0xffff; " \ 41 "setexpr fw_sz ${fw_sz} / 0x10000; " \ 42 "setexpr fw_sz ${fw_sz} * 0x10000; " \ 43 "sf erase 0x0 ${fw_sz}; " \ 44 "sf write ${loadaddr} 0x0 ${filesize}; " \ 45 "fi; " \ 46 "fi\0" \ 47 "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" 48 #else 49 #define UPDATE_M4_ENV "" 50 #endif 51 52 #define CONFIG_EXTRA_ENV_SETTINGS \ 53 UPDATE_M4_ENV \ 54 "script=boot.scr\0" \ 55 "image=zImage\0" \ 56 "console=ttymxc0\0" \ 57 "fdt_high=0xffffffff\0" \ 58 "initrd_high=0xffffffff\0" \ 59 "fdt_file=imx6sx-sdb.dtb\0" \ 60 "fdt_addr=0x88000000\0" \ 61 "boot_fdt=try\0" \ 62 "ip_dyn=yes\0" \ 63 "videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \ 64 "mmcdev=2\0" \ 65 "mmcpart=1\0" \ 66 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ 67 "mmcargs=setenv bootargs console=${console},${baudrate} " \ 68 "root=${mmcroot}\0" \ 69 "loadbootscript=" \ 70 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 71 "bootscript=echo Running bootscript from mmc ...; " \ 72 "source\0" \ 73 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 74 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 75 "mmcboot=echo Booting from mmc ...; " \ 76 "run mmcargs; " \ 77 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 78 "if run loadfdt; then " \ 79 "bootz ${loadaddr} - ${fdt_addr}; " \ 80 "else " \ 81 "if test ${boot_fdt} = try; then " \ 82 "bootz; " \ 83 "else " \ 84 "echo WARN: Cannot load the DT; " \ 85 "fi; " \ 86 "fi; " \ 87 "else " \ 88 "bootz; " \ 89 "fi;\0" \ 90 "netargs=setenv bootargs console=${console},${baudrate} " \ 91 "root=/dev/nfs " \ 92 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 93 "netboot=echo Booting from net ...; " \ 94 "run netargs; " \ 95 "if test ${ip_dyn} = yes; then " \ 96 "setenv get_cmd dhcp; " \ 97 "else " \ 98 "setenv get_cmd tftp; " \ 99 "fi; " \ 100 "${get_cmd} ${image}; " \ 101 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 102 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 103 "bootz ${loadaddr} - ${fdt_addr}; " \ 104 "else " \ 105 "if test ${boot_fdt} = try; then " \ 106 "bootz; " \ 107 "else " \ 108 "echo WARN: Cannot load the DT; " \ 109 "fi; " \ 110 "fi; " \ 111 "else " \ 112 "bootz; " \ 113 "fi;\0" 114 115 #define CONFIG_BOOTCOMMAND \ 116 "mmc dev ${mmcdev};" \ 117 "mmc dev ${mmcdev}; if mmc rescan; then " \ 118 "if run loadbootscript; then " \ 119 "run bootscript; " \ 120 "else " \ 121 "if run loadimage; then " \ 122 "run mmcboot; " \ 123 "else run netboot; " \ 124 "fi; " \ 125 "fi; " \ 126 "else run netboot; fi" 127 128 /* Miscellaneous configurable options */ 129 #define CONFIG_SYS_MEMTEST_START 0x80000000 130 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) 131 132 #define CONFIG_STACKSIZE SZ_128K 133 134 /* Physical Memory Map */ 135 #define CONFIG_NR_DRAM_BANKS 1 136 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 137 #define PHYS_SDRAM_SIZE SZ_1G 138 139 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 140 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 141 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 142 143 #define CONFIG_SYS_INIT_SP_OFFSET \ 144 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 145 #define CONFIG_SYS_INIT_SP_ADDR \ 146 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 147 148 /* MMC Configuration */ 149 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR 150 151 /* I2C Configs */ 152 #define CONFIG_CMD_I2C 153 #define CONFIG_SYS_I2C 154 #define CONFIG_SYS_I2C_MXC 155 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 156 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 157 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 158 #define CONFIG_SYS_I2C_SPEED 100000 159 160 /* PMIC */ 161 #define CONFIG_POWER 162 #define CONFIG_POWER_I2C 163 #define CONFIG_POWER_PFUZE100 164 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 165 166 /* Network */ 167 #define CONFIG_CMD_PING 168 #define CONFIG_CMD_DHCP 169 #define CONFIG_CMD_MII 170 #define CONFIG_FEC_MXC 171 #define CONFIG_MII 172 173 #define IMX_FEC_BASE ENET_BASE_ADDR 174 #define CONFIG_FEC_MXC_PHYADDR 0x1 175 176 #define CONFIG_FEC_XCV_TYPE RGMII 177 #define CONFIG_ETHPRIME "FEC" 178 179 #define CONFIG_PHYLIB 180 #define CONFIG_PHY_ATHEROS 181 182 183 #define CONFIG_CMD_USB 184 #ifdef CONFIG_CMD_USB 185 #define CONFIG_USB_EHCI 186 #define CONFIG_USB_EHCI_MX6 187 #define CONFIG_USB_STORAGE 188 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 189 #define CONFIG_USB_HOST_ETHER 190 #define CONFIG_USB_ETHER_ASIX 191 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 192 #define CONFIG_MXC_USB_FLAGS 0 193 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 194 #endif 195 196 #define CONFIG_CMD_PCI 197 #ifdef CONFIG_CMD_PCI 198 #define CONFIG_PCI 199 #define CONFIG_PCI_PNP 200 #define CONFIG_PCI_SCAN_SHOW 201 #define CONFIG_PCIE_IMX 202 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) 203 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) 204 #endif 205 206 #define CONFIG_IMX_THERMAL 207 208 #define CONFIG_CMD_TIME 209 210 211 #ifdef CONFIG_FSL_QSPI 212 #define CONFIG_CMD_SF 213 #define CONFIG_SYS_FSL_QSPI_LE 214 #define CONFIG_SYS_FSL_QSPI_AHB 215 #ifdef CONFIG_MX6SX_SABRESD_REVA 216 #define FSL_QSPI_FLASH_SIZE SZ_16M 217 #else 218 #define FSL_QSPI_FLASH_SIZE SZ_32M 219 #endif 220 #define FSL_QSPI_FLASH_NUM 2 221 #endif 222 223 #ifndef CONFIG_SPL_BUILD 224 #define CONFIG_VIDEO 225 #ifdef CONFIG_VIDEO 226 #define CONFIG_CFB_CONSOLE 227 #define CONFIG_VIDEO_MXS 228 #define CONFIG_VIDEO_LOGO 229 #define CONFIG_VIDEO_SW_CURSOR 230 #define CONFIG_VGA_AS_SINGLE_DEVICE 231 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 232 #define CONFIG_SPLASH_SCREEN 233 #define CONFIG_SPLASH_SCREEN_ALIGN 234 #define CONFIG_CMD_BMP 235 #define CONFIG_BMP_16BPP 236 #define CONFIG_VIDEO_BMP_RLE8 237 #define CONFIG_VIDEO_BMP_LOGO 238 #define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR 239 #endif 240 #endif 241 242 #define CONFIG_ENV_OFFSET (8 * SZ_64K) 243 #define CONFIG_ENV_SIZE SZ_8K 244 #define CONFIG_ENV_IS_IN_MMC 245 246 #define CONFIG_SYS_FSL_USDHC_NUM 3 247 #if defined(CONFIG_ENV_IS_IN_MMC) 248 #define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/ 249 #endif 250 251 #endif /* __CONFIG_H */ 252