1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the Freescale i.MX6SX Sabreauto board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "mx6_common.h" 13 14 /* Size of malloc() pool */ 15 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) 16 17 #define CONFIG_BOARD_EARLY_INIT_F 18 #define CONFIG_BOARD_LATE_INIT 19 20 #define CONFIG_MXC_UART 21 #define CONFIG_MXC_UART_BASE UART1_BASE 22 23 #define CONFIG_EXTRA_ENV_SETTINGS \ 24 "script=boot.scr\0" \ 25 "image=zImage\0" \ 26 "console=ttymxc0\0" \ 27 "fdt_high=0xffffffff\0" \ 28 "initrd_high=0xffffffff\0" \ 29 "fdt_file=imx6sx-sabreauto.dtb\0" \ 30 "fdt_addr=0x88000000\0" \ 31 "boot_fdt=try\0" \ 32 "ip_dyn=yes\0" \ 33 "mmcdev=0\0" \ 34 "mmcpart=1\0" \ 35 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ 36 "mmcargs=setenv bootargs console=${console},${baudrate} " \ 37 "root=${mmcroot}\0" \ 38 "loadbootscript=" \ 39 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 40 "bootscript=echo Running bootscript from mmc ...; " \ 41 "source\0" \ 42 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 43 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 44 "mmcboot=echo Booting from mmc ...; " \ 45 "run mmcargs; " \ 46 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 47 "if run loadfdt; then " \ 48 "bootz ${loadaddr} - ${fdt_addr}; " \ 49 "else " \ 50 "if test ${boot_fdt} = try; then " \ 51 "bootz; " \ 52 "else " \ 53 "echo WARN: Cannot load the DT; " \ 54 "fi; " \ 55 "fi; " \ 56 "else " \ 57 "bootz; " \ 58 "fi;\0" \ 59 "netargs=setenv bootargs console=${console},${baudrate} " \ 60 "root=/dev/nfs " \ 61 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 62 "netboot=echo Booting from net ...; " \ 63 "run netargs; " \ 64 "if test ${ip_dyn} = yes; then " \ 65 "setenv get_cmd dhcp; " \ 66 "else " \ 67 "setenv get_cmd tftp; " \ 68 "fi; " \ 69 "${get_cmd} ${image}; " \ 70 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 71 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 72 "bootz ${loadaddr} - ${fdt_addr}; " \ 73 "else " \ 74 "if test ${boot_fdt} = try; then " \ 75 "bootz; " \ 76 "else " \ 77 "echo WARN: Cannot load the DT; " \ 78 "fi; " \ 79 "fi; " \ 80 "else " \ 81 "bootz; " \ 82 "fi;\0" 83 84 #define CONFIG_BOOTCOMMAND \ 85 "mmc dev ${mmcdev};" \ 86 "mmc dev ${mmcdev}; if mmc rescan; then " \ 87 "if run loadbootscript; then " \ 88 "run bootscript; " \ 89 "else " \ 90 "if run loadimage; then " \ 91 "run mmcboot; " \ 92 "else run netboot; " \ 93 "fi; " \ 94 "fi; " \ 95 "else run netboot; fi" 96 97 /* Miscellaneous configurable options */ 98 #define CONFIG_SYS_MEMTEST_START 0x80000000 99 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) 100 101 #define CONFIG_STACKSIZE SZ_128K 102 103 /* Physical Memory Map */ 104 #define CONFIG_NR_DRAM_BANKS 1 105 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 106 107 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 108 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 109 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 110 111 #define CONFIG_SYS_INIT_SP_OFFSET \ 112 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 113 #define CONFIG_SYS_INIT_SP_ADDR \ 114 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 115 116 /* MMC Configuration */ 117 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR 118 119 /* I2C Configs */ 120 #define CONFIG_SYS_I2C 121 #define CONFIG_SYS_I2C_MXC 122 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 123 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 124 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 125 #define CONFIG_SYS_I2C_SPEED 100000 126 127 /* PMIC */ 128 #define CONFIG_POWER 129 #define CONFIG_POWER_I2C 130 #define CONFIG_POWER_PFUZE100 131 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 132 133 /* NAND flash command */ 134 #define CONFIG_CMD_NAND 135 #define CONFIG_CMD_NAND_TRIMFFS 136 137 /* NAND stuff */ 138 #define CONFIG_NAND_MXS 139 #define CONFIG_SYS_MAX_NAND_DEVICE 1 140 #define CONFIG_SYS_NAND_BASE 0x40000000 141 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 142 #define CONFIG_SYS_NAND_ONFI_DETECTION 143 144 /* DMA stuff, needed for GPMI/MXS NAND support */ 145 #define CONFIG_APBH_DMA 146 #define CONFIG_APBH_DMA_BURST 147 #define CONFIG_APBH_DMA_BURST8 148 149 /* Network */ 150 151 #define CONFIG_FEC_MXC 152 #define CONFIG_MII 153 154 #define IMX_FEC_BASE ENET2_BASE_ADDR 155 #define CONFIG_FEC_MXC_PHYADDR 0x0 156 157 #define CONFIG_FEC_XCV_TYPE RGMII 158 #define CONFIG_ETHPRIME "FEC" 159 160 #define CONFIG_PHYLIB 161 #define CONFIG_PHY_ATHEROS 162 163 #ifdef CONFIG_CMD_USB 164 #define CONFIG_USB_EHCI 165 #define CONFIG_USB_EHCI_MX6 166 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 167 #define CONFIG_USB_HOST_ETHER 168 #define CONFIG_USB_ETHER_ASIX 169 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 170 #define CONFIG_MXC_USB_FLAGS 0 171 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 172 #endif 173 174 #define CONFIG_IMX_THERMAL 175 176 #ifdef CONFIG_FSL_QSPI 177 #define CONFIG_SYS_FSL_QSPI_AHB 178 #define CONFIG_SF_DEFAULT_BUS 0 179 #define CONFIG_SF_DEFAULT_CS 0 180 #define CONFIG_SF_DEFAULT_SPEED 40000000 181 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 182 #define FSL_QSPI_FLASH_SIZE SZ_32M 183 #define FSL_QSPI_FLASH_NUM 2 184 #endif 185 186 #define CONFIG_ENV_OFFSET (8 * SZ_64K) 187 #define CONFIG_ENV_SIZE SZ_8K 188 #define CONFIG_ENV_IS_IN_MMC 189 190 #define CONFIG_SYS_FSL_USDHC_NUM 2 191 #if defined(CONFIG_ENV_IS_IN_MMC) 192 #define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/ 193 #endif 194 195 #define CONFIG_PCA953X 196 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } 197 198 #endif /* __CONFIG_H */ 199