1 /*
2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
3  *
4  * Configuration settings for the Freescale i.MX6Q SabreAuto board.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __MX6SABREAUTO_CONFIG_H
10 #define __MX6SABREAUTO_CONFIG_H
11 
12 #ifdef CONFIG_SPL
13 #include "imx6_spl.h"
14 #endif
15 
16 #define CONFIG_MACH_TYPE	3529
17 #define CONFIG_MXC_UART_BASE	UART4_BASE
18 #define CONSOLE_DEV		"ttymxc3"
19 
20 /* USB Configs */
21 #define CONFIG_USB_HOST_ETHER
22 #define CONFIG_USB_ETHER_ASIX
23 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
24 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
25 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
26 #define CONFIG_MXC_USB_FLAGS	0
27 
28 #define CONFIG_PCA953X
29 #define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x30, 8}, {0x32, 8}, {0x34, 8} }
30 
31 #include "mx6sabre_common.h"
32 
33 /* Falcon Mode */
34 #ifdef CONFIG_SPL_OS_BOOT
35 #define CONFIG_SPL_FS_LOAD_ARGS_NAME	"args"
36 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"uImage"
37 #define CONFIG_CMD_SPL
38 #define CONFIG_SYS_SPL_ARGS_ADDR       0x18000000
39 #define CONFIG_CMD_SPL_WRITE_SIZE      (128 * SZ_1K)
40 
41 /* Falcon Mode - MMC support: args@1MB kernel@2MB */
42 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR  0x800   /* 1MB */
43 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
44 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR        0x1000  /* 2MB */
45 #endif
46 
47 #ifdef CONFIG_MTD_NOR_FLASH
48 #define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
49 #define CONFIG_SYS_FLASH_SECT_SIZE      (128 * 1024)
50 #define CONFIG_SYS_MAX_FLASH_BANKS 1    /* max number of memory banks */
51 #define CONFIG_SYS_MAX_FLASH_SECT 256   /* max number of sectors on one chip */
52 #define CONFIG_SYS_FLASH_CFI            /* Flash memory is CFI compliant */
53 #define CONFIG_FLASH_CFI_DRIVER         /* Use drivers/cfi_flash.c */
54 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
55 #define CONFIG_SYS_FLASH_EMPTY_INFO
56 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
57 #endif
58 
59 #define CONFIG_SYS_FSL_USDHC_NUM	2
60 #if defined(CONFIG_ENV_IS_IN_MMC)
61 #define CONFIG_SYS_MMC_ENV_DEV		0
62 #endif
63 
64 /* I2C Configs */
65 #define CONFIG_SYS_I2C
66 #define CONFIG_SYS_I2C_MXC
67 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
68 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
69 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
70 #define CONFIG_SYS_I2C_SPEED		100000
71 
72 /* NAND flash command */
73 #define CONFIG_CMD_NAND
74 #define CONFIG_CMD_NAND_TRIMFFS
75 
76 /* NAND stuff */
77 #define CONFIG_NAND_MXS
78 #define CONFIG_SYS_MAX_NAND_DEVICE     1
79 #define CONFIG_SYS_NAND_BASE           0x40000000
80 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
81 #define CONFIG_SYS_NAND_ONFI_DETECTION
82 
83 /* DMA stuff, needed for GPMI/MXS NAND support */
84 #define CONFIG_APBH_DMA
85 #define CONFIG_APBH_DMA_BURST
86 #define CONFIG_APBH_DMA_BURST8
87 
88 /* PMIC */
89 #define CONFIG_POWER
90 #define CONFIG_POWER_I2C
91 #define CONFIG_POWER_PFUZE100
92 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
93 
94 #endif                         /* __MX6SABREAUTO_CONFIG_H */
95