1 /* 2 * Copyright (C) 2012 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the Freescale i.MX6Q SabreAuto board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __MX6SABREAUTO_CONFIG_H 10 #define __MX6SABREAUTO_CONFIG_H 11 12 #ifdef CONFIG_SPL 13 #include "imx6_spl.h" 14 #endif 15 16 #define CONFIG_MACH_TYPE 3529 17 #define CONFIG_MXC_UART_BASE UART4_BASE 18 #define CONSOLE_DEV "ttymxc3" 19 #define CONFIG_MMCROOT "/dev/mmcblk0p2" 20 21 /* USB Configs */ 22 #define CONFIG_USB_HOST_ETHER 23 #define CONFIG_USB_ETHER_ASIX 24 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 25 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 26 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 27 #define CONFIG_MXC_USB_FLAGS 0 28 29 #define CONFIG_PCA953X 30 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } 31 32 #include "mx6sabre_common.h" 33 34 #ifdef CONFIG_MTD_NOR_FLASH 35 #define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR 36 #define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) 37 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 38 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 39 #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ 40 #define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ 41 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ 42 #define CONFIG_SYS_FLASH_EMPTY_INFO 43 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 44 #endif 45 46 #define CONFIG_SYS_FSL_USDHC_NUM 2 47 #if defined(CONFIG_ENV_IS_IN_MMC) 48 #define CONFIG_SYS_MMC_ENV_DEV 0 49 #endif 50 51 /* I2C Configs */ 52 #define CONFIG_SYS_I2C 53 #define CONFIG_SYS_I2C_MXC 54 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 55 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 56 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 57 #define CONFIG_SYS_I2C_SPEED 100000 58 59 /* NAND flash command */ 60 #define CONFIG_CMD_NAND 61 #define CONFIG_CMD_NAND_TRIMFFS 62 63 /* NAND stuff */ 64 #define CONFIG_NAND_MXS 65 #define CONFIG_SYS_MAX_NAND_DEVICE 1 66 #define CONFIG_SYS_NAND_BASE 0x40000000 67 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 68 #define CONFIG_SYS_NAND_ONFI_DETECTION 69 70 /* DMA stuff, needed for GPMI/MXS NAND support */ 71 #define CONFIG_APBH_DMA 72 #define CONFIG_APBH_DMA_BURST 73 #define CONFIG_APBH_DMA_BURST8 74 75 /* PMIC */ 76 #define CONFIG_POWER 77 #define CONFIG_POWER_I2C 78 #define CONFIG_POWER_PFUZE100 79 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 80 81 #endif /* __MX6SABREAUTO_CONFIG_H */ 82