1 /* 2 * Copyright (C) 2012 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the Freescale i.MX6Q SabreAuto board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __MX6SABREAUTO_CONFIG_H 10 #define __MX6SABREAUTO_CONFIG_H 11 12 #ifdef CONFIG_SPL 13 #include "imx6_spl.h" 14 #endif 15 16 #define CONFIG_MACH_TYPE 3529 17 #define CONFIG_MXC_UART_BASE UART4_BASE 18 #define CONSOLE_DEV "ttymxc3" 19 20 /* USB Configs */ 21 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 22 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 23 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 24 #define CONFIG_MXC_USB_FLAGS 0 25 26 #define CONFIG_PCA953X 27 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } 28 29 #include "mx6sabre_common.h" 30 31 /* Falcon Mode */ 32 #ifdef CONFIG_SPL_OS_BOOT 33 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 34 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 35 #define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 36 37 /* Falcon Mode - MMC support: args@1MB kernel@2MB */ 38 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ 39 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) 40 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ 41 #endif 42 43 #ifdef CONFIG_MTD_NOR_FLASH 44 #define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR 45 #define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) 46 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 47 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 48 #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ 49 #define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ 50 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ 51 #define CONFIG_SYS_FLASH_EMPTY_INFO 52 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 53 #endif 54 55 #define CONFIG_SYS_FSL_USDHC_NUM 2 56 #if defined(CONFIG_ENV_IS_IN_MMC) 57 #define CONFIG_SYS_MMC_ENV_DEV 0 58 #endif 59 60 /* I2C Configs */ 61 #define CONFIG_SYS_I2C 62 #define CONFIG_SYS_I2C_MXC 63 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 64 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 65 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 66 #define CONFIG_SYS_I2C_SPEED 100000 67 68 /* NAND stuff */ 69 #define CONFIG_NAND_MXS 70 #define CONFIG_SYS_MAX_NAND_DEVICE 1 71 #define CONFIG_SYS_NAND_BASE 0x40000000 72 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 73 #define CONFIG_SYS_NAND_ONFI_DETECTION 74 75 /* DMA stuff, needed for GPMI/MXS NAND support */ 76 #define CONFIG_APBH_DMA 77 #define CONFIG_APBH_DMA_BURST 78 #define CONFIG_APBH_DMA_BURST8 79 80 /* PMIC */ 81 #define CONFIG_POWER 82 #define CONFIG_POWER_I2C 83 #define CONFIG_POWER_PFUZE100 84 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 85 86 #endif /* __MX6SABREAUTO_CONFIG_H */ 87