1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the MX53SMD Freescale board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD 13 14 #include <asm/arch/imx-regs.h> 15 16 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 17 #define CONFIG_SETUP_MEMORY_TAGS 18 #define CONFIG_INITRD_TAG 19 #define CONFIG_REVISION_TAG 20 21 #define CONFIG_SYS_FSL_CLK 22 23 /* Size of malloc() pool */ 24 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) 25 26 #define CONFIG_MXC_UART 27 #define CONFIG_MXC_UART_BASE UART1_BASE 28 29 /* I2C Configs */ 30 #define CONFIG_SYS_I2C 31 #define CONFIG_SYS_I2C_MXC 32 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 33 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 34 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 35 36 /* MMC Configs */ 37 #define CONFIG_FSL_ESDHC 38 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 39 #define CONFIG_SYS_FSL_ESDHC_NUM 1 40 41 /* Eth Configs */ 42 #define CONFIG_HAS_ETH1 43 #define CONFIG_MII 44 45 #define CONFIG_FEC_MXC 46 #define IMX_FEC_BASE FEC_BASE_ADDR 47 #define CONFIG_FEC_MXC_PHYADDR 0x1F 48 49 /* allow to overwrite serial and ethaddr */ 50 #define CONFIG_ENV_OVERWRITE 51 #define CONFIG_CONS_INDEX 1 52 53 /* Command definition */ 54 55 #define CONFIG_ETHPRIME "FEC0" 56 57 #define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ 58 #define CONFIG_SYS_TEXT_BASE 0x77800000 59 60 #define CONFIG_EXTRA_ENV_SETTINGS \ 61 "script=boot.scr\0" \ 62 "uimage=uImage\0" \ 63 "mmcdev=0\0" \ 64 "mmcpart=2\0" \ 65 "mmcroot=/dev/mmcblk0p3 rw\0" \ 66 "mmcrootfstype=ext3 rootwait\0" \ 67 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ 68 "root=${mmcroot} " \ 69 "rootfstype=${mmcrootfstype}\0" \ 70 "loadbootscript=" \ 71 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 72 "bootscript=echo Running bootscript from mmc ...; " \ 73 "source\0" \ 74 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ 75 "mmcboot=echo Booting from mmc ...; " \ 76 "run mmcargs; " \ 77 "bootm\0" \ 78 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ 79 "root=/dev/nfs " \ 80 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 81 "netboot=echo Booting from net ...; " \ 82 "run netargs; " \ 83 "dhcp ${uimage}; bootm\0" \ 84 85 #define CONFIG_BOOTCOMMAND \ 86 "mmc dev ${mmcdev}; if mmc rescan; then " \ 87 "if run loadbootscript; then " \ 88 "run bootscript; " \ 89 "else " \ 90 "if run loaduimage; then " \ 91 "run mmcboot; " \ 92 "else run netboot; " \ 93 "fi; " \ 94 "fi; " \ 95 "else run netboot; fi" 96 #define CONFIG_ARP_TIMEOUT 200UL 97 98 /* Miscellaneous configurable options */ 99 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 100 #define CONFIG_AUTO_COMPLETE 101 102 #define CONFIG_SYS_MEMTEST_START 0x70000000 103 #define CONFIG_SYS_MEMTEST_END 0x70010000 104 105 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 106 107 #define CONFIG_CMDLINE_EDITING 108 109 /* Physical Memory Map */ 110 #define CONFIG_NR_DRAM_BANKS 2 111 #define PHYS_SDRAM_1 CSD0_BASE_ADDR 112 #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) 113 #define PHYS_SDRAM_2 CSD1_BASE_ADDR 114 #define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) 115 #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) 116 117 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) 118 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) 119 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) 120 121 #define CONFIG_SYS_INIT_SP_OFFSET \ 122 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 123 #define CONFIG_SYS_INIT_SP_ADDR \ 124 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 125 126 /* environment organization */ 127 #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 128 #define CONFIG_ENV_SIZE (8 * 1024) 129 #define CONFIG_SYS_MMC_ENV_DEV 0 130 131 #endif /* __CONFIG_H */ 132