1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the MX53SMD Freescale board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_MX53 13 14 #define CONFIG_DISPLAY_CPUINFO 15 #define CONFIG_DISPLAY_BOARDINFO 16 17 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD 18 19 #include <asm/arch/imx-regs.h> 20 21 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 22 #define CONFIG_SETUP_MEMORY_TAGS 23 #define CONFIG_INITRD_TAG 24 #define CONFIG_REVISION_TAG 25 26 #define CONFIG_SYS_FSL_CLK 27 28 /* Size of malloc() pool */ 29 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) 30 31 #define CONFIG_BOARD_EARLY_INIT_F 32 #define CONFIG_MXC_GPIO 33 34 #define CONFIG_MXC_UART 35 #define CONFIG_MXC_UART_BASE UART1_BASE 36 37 /* I2C Configs */ 38 #define CONFIG_CMD_I2C 39 #define CONFIG_SYS_I2C 40 #define CONFIG_SYS_I2C_MXC 41 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 42 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 43 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 44 45 /* MMC Configs */ 46 #define CONFIG_FSL_ESDHC 47 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 48 #define CONFIG_SYS_FSL_ESDHC_NUM 1 49 50 #define CONFIG_MMC 51 #define CONFIG_CMD_MMC 52 #define CONFIG_GENERIC_MMC 53 #define CONFIG_CMD_FAT 54 #define CONFIG_DOS_PARTITION 55 56 /* Eth Configs */ 57 #define CONFIG_HAS_ETH1 58 #define CONFIG_MII 59 60 #define CONFIG_FEC_MXC 61 #define IMX_FEC_BASE FEC_BASE_ADDR 62 #define CONFIG_FEC_MXC_PHYADDR 0x1F 63 64 #define CONFIG_CMD_PING 65 #define CONFIG_CMD_DHCP 66 #define CONFIG_CMD_MII 67 68 /* allow to overwrite serial and ethaddr */ 69 #define CONFIG_ENV_OVERWRITE 70 #define CONFIG_CONS_INDEX 1 71 #define CONFIG_BAUDRATE 115200 72 73 /* Command definition */ 74 #define CONFIG_BOOTDELAY 3 75 76 #define CONFIG_ETHPRIME "FEC0" 77 78 #define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ 79 #define CONFIG_SYS_TEXT_BASE 0x77800000 80 81 #define CONFIG_EXTRA_ENV_SETTINGS \ 82 "script=boot.scr\0" \ 83 "uimage=uImage\0" \ 84 "mmcdev=0\0" \ 85 "mmcpart=2\0" \ 86 "mmcroot=/dev/mmcblk0p3 rw\0" \ 87 "mmcrootfstype=ext3 rootwait\0" \ 88 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ 89 "root=${mmcroot} " \ 90 "rootfstype=${mmcrootfstype}\0" \ 91 "loadbootscript=" \ 92 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 93 "bootscript=echo Running bootscript from mmc ...; " \ 94 "source\0" \ 95 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ 96 "mmcboot=echo Booting from mmc ...; " \ 97 "run mmcargs; " \ 98 "bootm\0" \ 99 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ 100 "root=/dev/nfs " \ 101 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 102 "netboot=echo Booting from net ...; " \ 103 "run netargs; " \ 104 "dhcp ${uimage}; bootm\0" \ 105 106 #define CONFIG_BOOTCOMMAND \ 107 "mmc dev ${mmcdev}; if mmc rescan; then " \ 108 "if run loadbootscript; then " \ 109 "run bootscript; " \ 110 "else " \ 111 "if run loaduimage; then " \ 112 "run mmcboot; " \ 113 "else run netboot; " \ 114 "fi; " \ 115 "fi; " \ 116 "else run netboot; fi" 117 #define CONFIG_ARP_TIMEOUT 200UL 118 119 /* Miscellaneous configurable options */ 120 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 121 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 122 #define CONFIG_AUTO_COMPLETE 123 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 124 125 /* Print Buffer Size */ 126 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 127 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 128 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 129 130 #define CONFIG_SYS_MEMTEST_START 0x70000000 131 #define CONFIG_SYS_MEMTEST_END 0x70010000 132 133 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 134 135 #define CONFIG_CMDLINE_EDITING 136 137 /* Physical Memory Map */ 138 #define CONFIG_NR_DRAM_BANKS 2 139 #define PHYS_SDRAM_1 CSD0_BASE_ADDR 140 #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) 141 #define PHYS_SDRAM_2 CSD1_BASE_ADDR 142 #define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) 143 #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) 144 145 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) 146 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) 147 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) 148 149 #define CONFIG_SYS_INIT_SP_OFFSET \ 150 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 151 #define CONFIG_SYS_INIT_SP_ADDR \ 152 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 153 154 /* FLASH and environment organization */ 155 #define CONFIG_SYS_NO_FLASH 156 157 #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 158 #define CONFIG_ENV_SIZE (8 * 1024) 159 #define CONFIG_ENV_IS_IN_MMC 160 #define CONFIG_SYS_MMC_ENV_DEV 0 161 162 #define CONFIG_OF_LIBFDT 163 164 #endif /* __CONFIG_H */ 165