1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * Jason Liu <r64343@freescale.com> 4 * 5 * Configuration settings for Freescale MX53 low cost board. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <asm/arch/imx-regs.h> 14 15 #define CONSOLE_DEV "ttymxc0" 16 17 #define CONFIG_CMDLINE_TAG 18 #define CONFIG_SETUP_MEMORY_TAGS 19 #define CONFIG_INITRD_TAG 20 21 #define CONFIG_SYS_FSL_CLK 22 23 /* Size of malloc() pool */ 24 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 25 26 #define CONFIG_HW_WATCHDOG 27 #define CONFIG_IMX_WATCHDOG 28 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000 29 30 #define CONFIG_MISC_INIT_R 31 #define CONFIG_BOARD_LATE_INIT 32 #define CONFIG_REVISION_TAG 33 34 #define CONFIG_MXC_UART 35 #define CONFIG_MXC_UART_BASE UART1_BASE 36 37 /* MMC Configs */ 38 #define CONFIG_FSL_ESDHC 39 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 40 #define CONFIG_SYS_FSL_ESDHC_NUM 2 41 42 #define CONFIG_SUPPORT_RAW_INITRD /* bootz raw initrd support */ 43 44 /* Eth Configs */ 45 #define CONFIG_MII 46 47 #define CONFIG_FEC_MXC 48 #define IMX_FEC_BASE FEC_BASE_ADDR 49 #define CONFIG_FEC_MXC_PHYADDR 0x1F 50 51 /* USB Configs */ 52 #define CONFIG_USB_EHCI_MX5 53 #define CONFIG_USB_HOST_ETHER 54 #define CONFIG_USB_ETHER_ASIX 55 #define CONFIG_USB_ETHER_MCS7830 56 #define CONFIG_USB_ETHER_SMSC95XX 57 #define CONFIG_MXC_USB_PORT 1 58 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 59 #define CONFIG_MXC_USB_FLAGS 0 60 61 #define CONFIG_SYS_RTC_BUS_NUM 2 62 #define CONFIG_SYS_I2C_RTC_ADDR 0x30 63 64 /* I2C Configs */ 65 #define CONFIG_SYS_I2C 66 #define CONFIG_SYS_I2C_MXC 67 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 68 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 69 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 70 71 /* PMIC Controller */ 72 #define CONFIG_POWER 73 #define CONFIG_POWER_I2C 74 #define CONFIG_DIALOG_POWER 75 #define CONFIG_POWER_FSL 76 #define CONFIG_POWER_FSL_MC13892 77 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 78 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 79 80 /* allow to overwrite serial and ethaddr */ 81 #define CONFIG_ENV_OVERWRITE 82 #define CONFIG_CONS_INDEX 1 83 #define CONFIG_BAUDRATE 115200 84 85 /* Command definition */ 86 #define CONFIG_SUPPORT_RAW_INITRD 87 88 #define CONFIG_ETHPRIME "FEC0" 89 90 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ 91 92 #define PPD_CONFIG_NFS \ 93 "nfsserver=192.168.252.95\0" \ 94 "gatewayip=192.168.252.95\0" \ 95 "netmask=255.255.255.0\0" \ 96 "ipaddr=192.168.252.99\0" \ 97 "kernsize=0x2000\0" \ 98 "use_dhcp=0\0" \ 99 "nfsroot=/opt/springdale/rd\0" \ 100 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ 101 "${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \ 102 "choose_ip=if test $use_dhcp = 1; then set kern_ipconf ip=dhcp; " \ 103 "set getcmd dhcp; else set kern_ipconf " \ 104 "ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; " \ 105 "set getcmd tftp; fi\0" \ 106 "nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \ 107 "${nfsserver}:${image}; bootm ${loadaddr}\0" \ 108 109 #define CONFIG_EXTRA_ENV_SETTINGS \ 110 PPD_CONFIG_NFS \ 111 "bootlimit=10\0" \ 112 "image=/boot/fitImage\0" \ 113 "fdt_high=0xffffffff\0" \ 114 "dev=mmc\0" \ 115 "devnum=0\0" \ 116 "rootdev=mmcblk0p\0" \ 117 "quiet=quiet loglevel=0\0" \ 118 "console=" CONSOLE_DEV "\0" \ 119 "lvds=ldb\0" \ 120 "setargs=setenv bootargs ${lvds} jtag=on mem=2G " \ 121 "vt.global_cursor_default=0 bootcause=${bootcause} ${quiet} " \ 122 "console=${console} ${rtc_status}\0" \ 123 "bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} ro " \ 124 "rootwait ${bootargs}\0" \ 125 "doquiet=if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \ 126 "then setenv quiet; fi\0" \ 127 "hasfirstboot=ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \ 128 "/boot/bootcause/firstboot\0" \ 129 "swappartitions=setexpr partnum 3 - ${partnum}\0" \ 130 "failbootcmd=" \ 131 "ppd_lcd_enable; " \ 132 "msg=\"Monitor failed to start. " \ 133 "Try again, or contact GE Service for support.\"; " \ 134 "echo $msg; " \ 135 "setenv stdout vga; " \ 136 "echo \"\n\n\n\n \" $msg; " \ 137 "setenv stdout serial; " \ 138 "mw.b 0x7000A000 0xbc; " \ 139 "mw.b 0x7000A001 0x00; " \ 140 "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \ 141 "altbootcmd=" \ 142 "run doquiet; " \ 143 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ 144 "run hasfirstboot || setenv partnum 0; " \ 145 "if test ${partnum} != 0; then " \ 146 "setenv bootcause REVERT; " \ 147 "run swappartitions loadimage doboot; " \ 148 "fi; " \ 149 "run failbootcmd\0" \ 150 "loadimage=" \ 151 "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ 152 "doboot=" \ 153 "echo Booting from ${dev}:${devnum}:${partnum} ...; " \ 154 "run setargs; " \ 155 "run bootargs_emmc; " \ 156 "bootm ${loadaddr}\0" \ 157 "tryboot=" \ 158 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ 159 "run loadimage || run swappartitions && run loadimage || " \ 160 "setenv partnum 0 && echo MISSING IMAGE;" \ 161 "run doboot; " \ 162 "run failbootcmd\0" \ 163 "video-mode=" \ 164 "lcd:800x480-24@60,monitor=lcd\0" \ 165 166 #define CONFIG_MMCBOOTCOMMAND \ 167 "if mmc dev ${devnum}; then " \ 168 "run doquiet; " \ 169 "run tryboot; " \ 170 "fi; " \ 171 172 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 173 174 #define CONFIG_ARP_TIMEOUT 200UL 175 176 /* Miscellaneous configurable options */ 177 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 178 #define CONFIG_AUTO_COMPLETE 179 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 180 181 #define CONFIG_SYS_MAXARGS 48 /* max number of command args */ 182 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 183 184 #define CONFIG_SYS_MEMTEST_START 0x70000000 185 #define CONFIG_SYS_MEMTEST_END 0x70010000 186 187 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 188 189 #define CONFIG_CMDLINE_EDITING 190 191 /* Physical Memory Map */ 192 #define CONFIG_NR_DRAM_BANKS 2 193 #define PHYS_SDRAM_1 CSD0_BASE_ADDR 194 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) 195 #define PHYS_SDRAM_2 CSD1_BASE_ADDR 196 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) 197 #define PHYS_SDRAM_SIZE (gd->ram_size) 198 199 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) 200 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) 201 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) 202 203 #define CONFIG_SYS_INIT_SP_OFFSET \ 204 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 205 #define CONFIG_SYS_INIT_SP_ADDR \ 206 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 207 208 /* FLASH and environment organization */ 209 #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 210 #define CONFIG_ENV_SIZE (8 * 1024) 211 #define CONFIG_ENV_IS_IN_MMC 212 #define CONFIG_SYS_MMC_ENV_DEV 0 213 214 #define CONFIG_CMD_FUSE 215 #define CONFIG_FSL_IIM 216 217 #define CONFIG_SYS_I2C_SPEED 100000 218 219 /* I2C1 */ 220 #define CONFIG_SYS_NUM_I2C_BUSES 9 221 #define CONFIG_SYS_I2C_MAX_HOPS 1 222 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 223 {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \ 224 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ 225 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ 226 {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \ 227 {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \ 228 {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \ 229 {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \ 230 {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \ 231 } 232 233 #define CONFIG_BCH 234 235 /* Backlight Control */ 236 #define CONFIG_PWM_IMX 237 #define CONFIG_IMX6_PWM_PER_CLK 66666000 238 239 /* Framebuffer and LCD */ 240 #ifdef CONFIG_VIDEO 241 #define CONFIG_VIDEO_IPUV3 242 #endif 243 244 #endif /* __CONFIG_H */ 245