xref: /openbmc/u-boot/include/configs/mx53loco.h (revision be3b51aa)
1 /*
2  * Copyright (C) 2011 Freescale Semiconductor, Inc.
3  * Jason Liu <r64343@freescale.com>
4  *
5  * Configuration settings for Freescale MX53 low cost board.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #ifndef __CONFIG_H
24 #define __CONFIG_H
25 
26 #define CONFIG_MX53
27 
28 #define CONFIG_DISPLAY_BOARDINFO
29 
30 #define CONFIG_MACH_TYPE	MACH_TYPE_MX53_LOCO
31 
32 #include <asm/arch/imx-regs.h>
33 
34 #define CONFIG_CMDLINE_TAG
35 #define CONFIG_SETUP_MEMORY_TAGS
36 #define CONFIG_INITRD_TAG
37 
38 /* Size of malloc() pool */
39 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
40 
41 #define CONFIG_BOARD_EARLY_INIT_F
42 #define CONFIG_MXC_GPIO
43 #define CONFIG_REVISION_TAG
44 
45 #define CONFIG_MXC_UART
46 #define CONFIG_MXC_UART_BASE	UART1_BASE
47 
48 /* MMC Configs */
49 #define CONFIG_FSL_ESDHC
50 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
51 #define CONFIG_SYS_FSL_ESDHC_NUM	2
52 
53 #define CONFIG_MMC
54 #define CONFIG_CMD_MMC
55 #define CONFIG_GENERIC_MMC
56 #define CONFIG_CMD_FAT
57 #define CONFIG_CMD_EXT2
58 #define CONFIG_DOS_PARTITION
59 
60 /* Eth Configs */
61 #define CONFIG_MII
62 
63 #define CONFIG_FEC_MXC
64 #define IMX_FEC_BASE	FEC_BASE_ADDR
65 #define CONFIG_FEC_MXC_PHYADDR	0x1F
66 
67 #define CONFIG_CMD_PING
68 #define CONFIG_CMD_DHCP
69 #define CONFIG_CMD_MII
70 #define CONFIG_CMD_NET
71 
72 /* USB Configs */
73 #define CONFIG_CMD_USB
74 #define CONFIG_CMD_FAT
75 #define CONFIG_USB_EHCI
76 #define CONFIG_USB_EHCI_MX5
77 #define CONFIG_USB_STORAGE
78 #define CONFIG_USB_HOST_ETHER
79 #define CONFIG_USB_ETHER_ASIX
80 #define CONFIG_USB_ETHER_SMSC95XX
81 #define CONFIG_MXC_USB_PORT	1
82 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
83 #define CONFIG_MXC_USB_FLAGS	0
84 
85 /* I2C Configs */
86 #define CONFIG_HARD_I2C
87 #define CONFIG_I2C_MXC
88 #define CONFIG_SYS_I2C_BASE		I2C1_BASE_ADDR
89 #define CONFIG_SYS_I2C_SPEED		100000
90 
91 /* PMIC Controller */
92 #define CONFIG_POWER
93 #define CONFIG_POWER_I2C
94 #define CONFIG_DIALOG_PMIC
95 #define CONFIG_POWER_FSL
96 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR	0x48
97 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x8
98 
99 /* allow to overwrite serial and ethaddr */
100 #define CONFIG_ENV_OVERWRITE
101 #define CONFIG_CONS_INDEX		1
102 #define CONFIG_BAUDRATE			115200
103 
104 /* Command definition */
105 #include <config_cmd_default.h>
106 
107 #undef CONFIG_CMD_IMLS
108 
109 #define CONFIG_BOOTDELAY	3
110 
111 #define CONFIG_ETHPRIME		"FEC0"
112 
113 #define CONFIG_LOADADDR		0x70800000	/* loadaddr env var */
114 #define CONFIG_SYS_TEXT_BASE    0x77800000
115 
116 #define CONFIG_EXTRA_ENV_SETTINGS \
117 	"script=boot.scr\0" \
118 	"uimage=uImage\0" \
119 	"mmcdev=0\0" \
120 	"mmcpart=2\0" \
121 	"mmcroot=/dev/mmcblk0p3 rw\0" \
122 	"mmcrootfstype=ext3 rootwait\0" \
123 	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
124 		"root=${mmcroot} " \
125 		"rootfstype=${mmcrootfstype}\0" \
126 	"loadbootscript=" \
127 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
128 	"bootscript=echo Running bootscript from mmc ...; " \
129 		"source\0" \
130 	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
131 	"mmcboot=echo Booting from mmc ...; " \
132 		"run mmcargs; " \
133 		"bootm\0" \
134 	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
135 		"root=/dev/nfs " \
136 		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
137 	"netboot=echo Booting from net ...; " \
138 		"run netargs; " \
139 		"dhcp ${uimage}; bootm\0" \
140 
141 #define CONFIG_BOOTCOMMAND \
142 	"mmc dev ${mmcdev}; if mmc rescan; then " \
143 		"if run loadbootscript; then " \
144 			"run bootscript; " \
145 		"else " \
146 			"if run loaduimage; then " \
147 				"run mmcboot; " \
148 			"else run netboot; " \
149 			"fi; " \
150 		"fi; " \
151 	"else run netboot; fi"
152 
153 #define CONFIG_ARP_TIMEOUT	200UL
154 
155 /* Miscellaneous configurable options */
156 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
157 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
158 #define CONFIG_SYS_PROMPT		"MX53LOCO U-Boot > "
159 #define CONFIG_AUTO_COMPLETE
160 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
161 
162 /* Print Buffer Size */
163 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
164 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
165 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
166 
167 #define CONFIG_SYS_MEMTEST_START       0x70000000
168 #define CONFIG_SYS_MEMTEST_END         0x70010000
169 
170 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
171 
172 #define CONFIG_SYS_HZ		1000
173 #define CONFIG_CMDLINE_EDITING
174 
175 /* Physical Memory Map */
176 #define CONFIG_NR_DRAM_BANKS	2
177 #define PHYS_SDRAM_1		CSD0_BASE_ADDR
178 #define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
179 #define PHYS_SDRAM_2		CSD1_BASE_ADDR
180 #define PHYS_SDRAM_2_SIZE	(512 * 1024 * 1024)
181 #define PHYS_SDRAM_SIZE         (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
182 
183 #define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
184 #define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
185 #define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
186 
187 #define CONFIG_SYS_INIT_SP_OFFSET \
188 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
189 #define CONFIG_SYS_INIT_SP_ADDR \
190 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
191 
192 /* FLASH and environment organization */
193 #define CONFIG_SYS_NO_FLASH
194 
195 #define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
196 #define CONFIG_ENV_SIZE        (8 * 1024)
197 #define CONFIG_ENV_IS_IN_MMC
198 #define CONFIG_SYS_MMC_ENV_DEV 0
199 
200 #define CONFIG_OF_LIBFDT
201 
202 #define CONFIG_CMD_SATA
203 #ifdef CONFIG_CMD_SATA
204 	#define CONFIG_DWC_AHSATA
205 	#define CONFIG_SYS_SATA_MAX_DEVICE      1
206 	#define CONFIG_DWC_AHSATA_PORT_ID       0
207 	#define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_BASE_ADDR
208 	#define CONFIG_LBA48
209 	#define CONFIG_LIBATA
210 #endif
211 
212 /* Framebuffer and LCD */
213 #define CONFIG_PREBOOT
214 #define CONFIG_VIDEO
215 #define CONFIG_VIDEO_IPUV3
216 #define CONFIG_CFB_CONSOLE
217 #define CONFIG_VGA_AS_SINGLE_DEVICE
218 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
219 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
220 #define CONFIG_VIDEO_BMP_RLE8
221 #define CONFIG_SPLASH_SCREEN
222 #define CONFIG_BMP_16BPP
223 #define CONFIG_VIDEO_LOGO
224 #define CONFIG_IPUV3_CLK	200000000
225 
226 #endif				/* __CONFIG_H */
227