1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * Jason Liu <r64343@freescale.com> 4 * 5 * Configuration settings for Freescale MX53 low cost board. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO 14 15 #include <asm/arch/imx-regs.h> 16 17 #define CONFIG_CMDLINE_TAG 18 #define CONFIG_SETUP_MEMORY_TAGS 19 #define CONFIG_INITRD_TAG 20 21 #define CONFIG_SYS_FSL_CLK 22 23 /* Size of malloc() pool */ 24 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 25 26 #define CONFIG_REVISION_TAG 27 28 #define CONFIG_MXC_UART 29 #define CONFIG_MXC_UART_BASE UART1_BASE 30 31 /* MMC Configs */ 32 #define CONFIG_FSL_ESDHC 33 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 34 #define CONFIG_SYS_FSL_ESDHC_NUM 2 35 36 /* Eth Configs */ 37 #define CONFIG_MII 38 39 #define CONFIG_FEC_MXC 40 #define IMX_FEC_BASE FEC_BASE_ADDR 41 #define CONFIG_FEC_MXC_PHYADDR 0x1F 42 43 /* USB Configs */ 44 #define CONFIG_USB_EHCI_MX5 45 #define CONFIG_MXC_USB_PORT 1 46 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 47 #define CONFIG_MXC_USB_FLAGS 0 48 49 /* I2C Configs */ 50 #define CONFIG_SYS_I2C 51 #define CONFIG_SYS_I2C_MXC 52 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 53 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 54 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 55 56 /* PMIC Controller */ 57 #define CONFIG_POWER 58 #define CONFIG_POWER_I2C 59 #define CONFIG_DIALOG_POWER 60 #define CONFIG_POWER_FSL 61 #define CONFIG_POWER_FSL_MC13892 62 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 63 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 64 65 /* allow to overwrite serial and ethaddr */ 66 #define CONFIG_ENV_OVERWRITE 67 #define CONFIG_CONS_INDEX 1 68 69 /* Command definition */ 70 71 72 #define CONFIG_ETHPRIME "FEC0" 73 74 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ 75 76 #define CONFIG_EXTRA_ENV_SETTINGS \ 77 "script=boot.scr\0" \ 78 "image=zImage\0" \ 79 "fdt_addr=0x71000000\0" \ 80 "boot_fdt=try\0" \ 81 "ip_dyn=yes\0" \ 82 "mmcdev=0\0" \ 83 "mmcpart=1\0" \ 84 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ 85 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \ 86 "loadbootscript=" \ 87 "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 88 "bootscript=echo Running bootscript from mmc ...; " \ 89 "source\0" \ 90 "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 91 "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 92 "mmcboot=echo Booting from mmc ...; " \ 93 "run mmcargs; " \ 94 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 95 "if run loadfdt; then " \ 96 "bootz ${loadaddr} - ${fdt_addr}; " \ 97 "else " \ 98 "if test ${boot_fdt} = try; then " \ 99 "bootz; " \ 100 "else " \ 101 "echo WARN: Cannot load the DT; " \ 102 "fi; " \ 103 "fi; " \ 104 "else " \ 105 "bootz; " \ 106 "fi;\0" \ 107 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ 108 "root=/dev/nfs " \ 109 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 110 "netboot=echo Booting from net ...; " \ 111 "run netargs; " \ 112 "if test ${ip_dyn} = yes; then " \ 113 "setenv get_cmd dhcp; " \ 114 "else " \ 115 "setenv get_cmd tftp; " \ 116 "fi; " \ 117 "${get_cmd} ${image}; " \ 118 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 119 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 120 "bootz ${loadaddr} - ${fdt_addr}; " \ 121 "else " \ 122 "if test ${boot_fdt} = try; then " \ 123 "bootz; " \ 124 "else " \ 125 "echo ERROR: Cannot load the DT; " \ 126 "exit; " \ 127 "fi; " \ 128 "fi; " \ 129 "else " \ 130 "bootz; " \ 131 "fi;\0" 132 133 #define CONFIG_BOOTCOMMAND \ 134 "mmc dev ${mmcdev}; if mmc rescan; then " \ 135 "if run loadbootscript; then " \ 136 "run bootscript; " \ 137 "else " \ 138 "if run loadimage; then " \ 139 "run mmcboot; " \ 140 "else run netboot; " \ 141 "fi; " \ 142 "fi; " \ 143 "else run netboot; fi" 144 145 #define CONFIG_ARP_TIMEOUT 200UL 146 147 /* Miscellaneous configurable options */ 148 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 149 150 #define CONFIG_SYS_MEMTEST_START 0x70000000 151 #define CONFIG_SYS_MEMTEST_END 0x70010000 152 153 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 154 155 /* Physical Memory Map */ 156 #define CONFIG_NR_DRAM_BANKS 2 157 #define PHYS_SDRAM_1 CSD0_BASE_ADDR 158 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) 159 #define PHYS_SDRAM_2 CSD1_BASE_ADDR 160 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) 161 #define PHYS_SDRAM_SIZE (gd->ram_size) 162 163 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) 164 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) 165 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) 166 167 #define CONFIG_SYS_INIT_SP_OFFSET \ 168 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 169 #define CONFIG_SYS_INIT_SP_ADDR \ 170 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 171 172 /* environment organization */ 173 #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 174 #define CONFIG_ENV_SIZE (8 * 1024) 175 #define CONFIG_SYS_MMC_ENV_DEV 0 176 177 #ifdef CONFIG_CMD_SATA 178 #define CONFIG_SYS_SATA_MAX_DEVICE 1 179 #define CONFIG_DWC_AHSATA_PORT_ID 0 180 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR 181 #define CONFIG_LBA48 182 #endif 183 184 /* Framebuffer and LCD */ 185 #define CONFIG_PREBOOT 186 #define CONFIG_VIDEO_IPUV3 187 #define CONFIG_VIDEO_BMP_RLE8 188 #define CONFIG_SPLASH_SCREEN 189 #define CONFIG_BMP_16BPP 190 #define CONFIG_VIDEO_LOGO 191 192 #endif /* __CONFIG_H */ 193