1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * Jason Liu <r64343@freescale.com> 4 * 5 * Configuration settings for Freescale MX53 low cost board. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_MX53 14 15 #define CONFIG_DISPLAY_BOARDINFO 16 17 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO 18 19 #include <asm/arch/imx-regs.h> 20 21 #define CONFIG_CMDLINE_TAG 22 #define CONFIG_SETUP_MEMORY_TAGS 23 #define CONFIG_INITRD_TAG 24 25 #define CONFIG_SYS_FSL_CLK 26 27 /* Size of malloc() pool */ 28 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 29 30 #define CONFIG_BOARD_EARLY_INIT_F 31 #define CONFIG_BOARD_LATE_INIT 32 #define CONFIG_MXC_GPIO 33 #define CONFIG_REVISION_TAG 34 35 #define CONFIG_MXC_UART 36 #define CONFIG_MXC_UART_BASE UART1_BASE 37 38 /* MMC Configs */ 39 #define CONFIG_FSL_ESDHC 40 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 41 #define CONFIG_SYS_FSL_ESDHC_NUM 2 42 43 #define CONFIG_MMC 44 #define CONFIG_GENERIC_MMC 45 #define CONFIG_DOS_PARTITION 46 47 /* Eth Configs */ 48 #define CONFIG_MII 49 50 #define CONFIG_FEC_MXC 51 #define IMX_FEC_BASE FEC_BASE_ADDR 52 #define CONFIG_FEC_MXC_PHYADDR 0x1F 53 54 /* USB Configs */ 55 #define CONFIG_USB_EHCI 56 #define CONFIG_USB_EHCI_MX5 57 #define CONFIG_USB_HOST_ETHER 58 #define CONFIG_USB_ETHER_ASIX 59 #define CONFIG_USB_ETHER_MCS7830 60 #define CONFIG_USB_ETHER_SMSC95XX 61 #define CONFIG_MXC_USB_PORT 1 62 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 63 #define CONFIG_MXC_USB_FLAGS 0 64 65 /* I2C Configs */ 66 #define CONFIG_SYS_I2C 67 #define CONFIG_SYS_I2C_MXC 68 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 69 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 70 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 71 72 /* PMIC Controller */ 73 #define CONFIG_POWER 74 #define CONFIG_POWER_I2C 75 #define CONFIG_DIALOG_POWER 76 #define CONFIG_POWER_FSL 77 #define CONFIG_POWER_FSL_MC13892 78 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 79 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 80 81 /* allow to overwrite serial and ethaddr */ 82 #define CONFIG_ENV_OVERWRITE 83 #define CONFIG_CONS_INDEX 1 84 #define CONFIG_BAUDRATE 115200 85 86 /* Command definition */ 87 #define CONFIG_SUPPORT_RAW_INITRD 88 89 90 #define CONFIG_ETHPRIME "FEC0" 91 92 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ 93 #define CONFIG_SYS_TEXT_BASE 0x77800000 94 95 #define CONFIG_EXTRA_ENV_SETTINGS \ 96 "script=boot.scr\0" \ 97 "image=zImage\0" \ 98 "fdt_addr=0x71000000\0" \ 99 "boot_fdt=try\0" \ 100 "ip_dyn=yes\0" \ 101 "mmcdev=0\0" \ 102 "mmcpart=1\0" \ 103 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ 104 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \ 105 "loadbootscript=" \ 106 "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 107 "bootscript=echo Running bootscript from mmc ...; " \ 108 "source\0" \ 109 "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 110 "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 111 "mmcboot=echo Booting from mmc ...; " \ 112 "run mmcargs; " \ 113 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 114 "if run loadfdt; then " \ 115 "bootz ${loadaddr} - ${fdt_addr}; " \ 116 "else " \ 117 "if test ${boot_fdt} = try; then " \ 118 "bootz; " \ 119 "else " \ 120 "echo WARN: Cannot load the DT; " \ 121 "fi; " \ 122 "fi; " \ 123 "else " \ 124 "bootz; " \ 125 "fi;\0" \ 126 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ 127 "root=/dev/nfs " \ 128 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 129 "netboot=echo Booting from net ...; " \ 130 "run netargs; " \ 131 "if test ${ip_dyn} = yes; then " \ 132 "setenv get_cmd dhcp; " \ 133 "else " \ 134 "setenv get_cmd tftp; " \ 135 "fi; " \ 136 "${get_cmd} ${image}; " \ 137 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 138 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 139 "bootz ${loadaddr} - ${fdt_addr}; " \ 140 "else " \ 141 "if test ${boot_fdt} = try; then " \ 142 "bootz; " \ 143 "else " \ 144 "echo ERROR: Cannot load the DT; " \ 145 "exit; " \ 146 "fi; " \ 147 "fi; " \ 148 "else " \ 149 "bootz; " \ 150 "fi;\0" 151 152 #define CONFIG_BOOTCOMMAND \ 153 "mmc dev ${mmcdev}; if mmc rescan; then " \ 154 "if run loadbootscript; then " \ 155 "run bootscript; " \ 156 "else " \ 157 "if run loadimage; then " \ 158 "run mmcboot; " \ 159 "else run netboot; " \ 160 "fi; " \ 161 "fi; " \ 162 "else run netboot; fi" 163 164 #define CONFIG_ARP_TIMEOUT 200UL 165 166 /* Miscellaneous configurable options */ 167 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 168 #define CONFIG_AUTO_COMPLETE 169 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 170 171 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 172 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 173 174 #define CONFIG_SYS_MEMTEST_START 0x70000000 175 #define CONFIG_SYS_MEMTEST_END 0x70010000 176 177 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 178 179 #define CONFIG_CMDLINE_EDITING 180 181 /* Physical Memory Map */ 182 #define CONFIG_NR_DRAM_BANKS 2 183 #define PHYS_SDRAM_1 CSD0_BASE_ADDR 184 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) 185 #define PHYS_SDRAM_2 CSD1_BASE_ADDR 186 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) 187 #define PHYS_SDRAM_SIZE (gd->ram_size) 188 189 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) 190 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) 191 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) 192 193 #define CONFIG_SYS_INIT_SP_OFFSET \ 194 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 195 #define CONFIG_SYS_INIT_SP_ADDR \ 196 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 197 198 /* FLASH and environment organization */ 199 #define CONFIG_SYS_NO_FLASH 200 201 #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 202 #define CONFIG_ENV_SIZE (8 * 1024) 203 #define CONFIG_ENV_IS_IN_MMC 204 #define CONFIG_SYS_MMC_ENV_DEV 0 205 206 #define CONFIG_CMD_SATA 207 #ifdef CONFIG_CMD_SATA 208 #define CONFIG_DWC_AHSATA 209 #define CONFIG_SYS_SATA_MAX_DEVICE 1 210 #define CONFIG_DWC_AHSATA_PORT_ID 0 211 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR 212 #define CONFIG_LBA48 213 #define CONFIG_LIBATA 214 #endif 215 216 /* Framebuffer and LCD */ 217 #define CONFIG_PREBOOT 218 #define CONFIG_VIDEO 219 #define CONFIG_VIDEO_IPUV3 220 #define CONFIG_CFB_CONSOLE 221 #define CONFIG_VGA_AS_SINGLE_DEVICE 222 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 223 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 224 #define CONFIG_VIDEO_BMP_RLE8 225 #define CONFIG_SPLASH_SCREEN 226 #define CONFIG_BMP_16BPP 227 #define CONFIG_VIDEO_LOGO 228 #define CONFIG_IPUV3_CLK 200000000 229 230 #endif /* __CONFIG_H */ 231