1 /* 2 * Copyright (C) 2010 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the MX53-EVK Freescale board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_MX53 13 14 #define CONFIG_DISPLAY_CPUINFO 15 #define CONFIG_DISPLAY_BOARDINFO 16 17 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_EVK 18 19 #include <asm/arch/imx-regs.h> 20 21 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 22 #define CONFIG_SETUP_MEMORY_TAGS 23 #define CONFIG_INITRD_TAG 24 #define CONFIG_REVISION_TAG 25 26 #define CONFIG_SYS_FSL_CLK 27 28 /* Size of malloc() pool */ 29 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) 30 31 #define CONFIG_BOARD_EARLY_INIT_F 32 #define CONFIG_BOARD_LATE_INIT 33 #define CONFIG_MXC_GPIO 34 35 #define CONFIG_MXC_UART 36 #define CONFIG_MXC_UART_BASE UART1_BASE 37 38 /* I2C Configs */ 39 #define CONFIG_SYS_I2C 40 #define CONFIG_SYS_I2C_MXC 41 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 42 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 43 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 44 45 /* PMIC Configs */ 46 #define CONFIG_POWER 47 #define CONFIG_POWER_I2C 48 #define CONFIG_POWER_FSL 49 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8 50 #define CONFIG_POWER_FSL_MC13892 51 #define CONFIG_RTC_MC13XXX 52 53 /* MMC Configs */ 54 #define CONFIG_FSL_ESDHC 55 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 56 #define CONFIG_SYS_FSL_ESDHC_NUM 2 57 58 #define CONFIG_MMC 59 #define CONFIG_GENERIC_MMC 60 #define CONFIG_DOS_PARTITION 61 62 /* Eth Configs */ 63 #define CONFIG_MII 64 65 #define CONFIG_FEC_MXC 66 #define IMX_FEC_BASE FEC_BASE_ADDR 67 #define CONFIG_FEC_MXC_PHYADDR 0x1F 68 69 #define CONFIG_CMD_DATE 70 71 /* Miscellaneous commands */ 72 #define CONFIG_CMD_BMODE 73 74 /* allow to overwrite serial and ethaddr */ 75 #define CONFIG_ENV_OVERWRITE 76 #define CONFIG_CONS_INDEX 1 77 #define CONFIG_BAUDRATE 115200 78 79 /* Command definition */ 80 #define CONFIG_BOOTDELAY 3 81 82 #define CONFIG_ETHPRIME "FEC0" 83 84 #define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ 85 #define CONFIG_SYS_TEXT_BASE 0x77800000 86 87 #define CONFIG_EXTRA_ENV_SETTINGS \ 88 "script=boot.scr\0" \ 89 "uimage=uImage\0" \ 90 "mmcdev=0\0" \ 91 "mmcpart=2\0" \ 92 "mmcroot=/dev/mmcblk0p3 rw\0" \ 93 "mmcrootfstype=ext3 rootwait\0" \ 94 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ 95 "root=${mmcroot} " \ 96 "rootfstype=${mmcrootfstype}\0" \ 97 "loadbootscript=" \ 98 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 99 "bootscript=echo Running bootscript from mmc ...; " \ 100 "source\0" \ 101 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ 102 "mmcboot=echo Booting from mmc ...; " \ 103 "run mmcargs; " \ 104 "bootm\0" \ 105 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ 106 "root=/dev/nfs " \ 107 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 108 "netboot=echo Booting from net ...; " \ 109 "run netargs; " \ 110 "dhcp ${uimage}; bootm\0" \ 111 112 #define CONFIG_BOOTCOMMAND \ 113 "mmc dev ${mmcdev}; if mmc rescan; then " \ 114 "if run loadbootscript; then " \ 115 "run bootscript; " \ 116 "else " \ 117 "if run loaduimage; then " \ 118 "run mmcboot; " \ 119 "else run netboot; " \ 120 "fi; " \ 121 "fi; " \ 122 "else run netboot; fi" 123 124 #define CONFIG_ARP_TIMEOUT 200UL 125 126 /* Miscellaneous configurable options */ 127 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 128 #define CONFIG_AUTO_COMPLETE 129 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 130 131 /* Print Buffer Size */ 132 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 133 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 134 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 135 136 #define CONFIG_SYS_MEMTEST_START 0x70000000 137 #define CONFIG_SYS_MEMTEST_END 0x70010000 138 139 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 140 141 #define CONFIG_CMDLINE_EDITING 142 143 /* Physical Memory Map */ 144 #define CONFIG_NR_DRAM_BANKS 1 145 #define PHYS_SDRAM_1 CSD0_BASE_ADDR 146 #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) 147 148 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) 149 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) 150 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) 151 152 #define CONFIG_SYS_INIT_SP_OFFSET \ 153 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 154 #define CONFIG_SYS_INIT_SP_ADDR \ 155 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 156 157 /* FLASH and environment organization */ 158 #define CONFIG_SYS_NO_FLASH 159 160 #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 161 #define CONFIG_ENV_SIZE (8 * 1024) 162 #define CONFIG_ENV_IS_IN_MMC 163 #define CONFIG_SYS_MMC_ENV_DEV 0 164 165 #endif /* __CONFIG_H */ 166