1 /* 2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * (C) Copyright 2009 Freescale Semiconductor, Inc. 5 * 6 * Configuration settings for the MX51EVK Board 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* High Level Configuration Options */ 15 16 #define CONFIG_SYS_FSL_CLK 17 #define CONFIG_SYS_TEXT_BASE 0x97800000 18 19 #include <asm/arch/imx-regs.h> 20 21 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 22 #define CONFIG_SETUP_MEMORY_TAGS 23 #define CONFIG_INITRD_TAG 24 #define CONFIG_REVISION_TAG 25 26 #define CONFIG_MACH_TYPE MACH_TYPE_MX51_BABBAGE 27 /* 28 * Size of malloc() pool 29 */ 30 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 31 32 /* 33 * Hardware drivers 34 */ 35 #define CONFIG_FSL_IIM 36 #define CONFIG_CMD_FUSE 37 38 #define CONFIG_MXC_UART 39 #define CONFIG_MXC_UART_BASE UART1_BASE 40 #define CONFIG_MXC_GPIO 41 42 /* 43 * SPI Configs 44 * */ 45 46 #define CONFIG_MXC_SPI 47 48 /* PMIC Controller */ 49 #define CONFIG_POWER 50 #define CONFIG_POWER_SPI 51 #define CONFIG_POWER_FSL 52 #define CONFIG_FSL_PMIC_BUS 0 53 #define CONFIG_FSL_PMIC_CS 0 54 #define CONFIG_FSL_PMIC_CLK 2500000 55 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 56 #define CONFIG_FSL_PMIC_BITLEN 32 57 #define CONFIG_RTC_MC13XXX 58 59 /* 60 * MMC Configs 61 * */ 62 #define CONFIG_FSL_ESDHC 63 #define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR 64 #define CONFIG_SYS_FSL_ESDHC_NUM 2 65 66 /* 67 * Eth Configs 68 */ 69 #define CONFIG_MII 70 71 #define CONFIG_FEC_MXC 72 #define IMX_FEC_BASE FEC_BASE_ADDR 73 #define CONFIG_FEC_MXC_PHYADDR 0x1F 74 75 /* USB Configs */ 76 #define CONFIG_USB_EHCI 77 #define CONFIG_USB_EHCI_MX5 78 #define CONFIG_USB_HOST_ETHER 79 #define CONFIG_USB_ETHER_ASIX 80 #define CONFIG_USB_ETHER_SMSC95XX 81 #define CONFIG_MXC_USB_PORT 1 82 #define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI 83 #define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED 84 85 /* Framebuffer and LCD */ 86 #define CONFIG_PREBOOT 87 #define CONFIG_VIDEO_IPUV3 88 #define CONFIG_VIDEO_BMP_RLE8 89 #define CONFIG_SPLASH_SCREEN 90 #define CONFIG_BMP_16BPP 91 #define CONFIG_VIDEO_LOGO 92 #define CONFIG_IPUV3_CLK 133000000 93 94 /* allow to overwrite serial and ethaddr */ 95 #define CONFIG_ENV_OVERWRITE 96 #define CONFIG_CONS_INDEX 1 97 98 #define CONFIG_ETHPRIME "FEC0" 99 100 #define CONFIG_LOADADDR 0x92000000 /* loadaddr env var */ 101 102 #define CONFIG_EXTRA_ENV_SETTINGS \ 103 "script=boot.scr\0" \ 104 "image=zImage\0" \ 105 "fdt_file=imx51-babbage.dtb\0" \ 106 "fdt_addr=0x91000000\0" \ 107 "boot_fdt=try\0" \ 108 "ip_dyn=yes\0" \ 109 "mmcdev=0\0" \ 110 "mmcpart=1\0" \ 111 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ 112 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ 113 "root=${mmcroot}\0" \ 114 "loadbootscript=" \ 115 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 116 "bootscript=echo Running bootscript from mmc ...; " \ 117 "source\0" \ 118 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 119 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 120 "mmcboot=echo Booting from mmc ...; " \ 121 "run mmcargs; " \ 122 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 123 "if run loadfdt; then " \ 124 "bootz ${loadaddr} - ${fdt_addr}; " \ 125 "else " \ 126 "if test ${boot_fdt} = try; then " \ 127 "bootz; " \ 128 "else " \ 129 "echo WARN: Cannot load the DT; " \ 130 "fi; " \ 131 "fi; " \ 132 "else " \ 133 "bootz; " \ 134 "fi;\0" \ 135 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ 136 "root=/dev/nfs " \ 137 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 138 "netboot=echo Booting from net ...; " \ 139 "run netargs; " \ 140 "if test ${ip_dyn} = yes; then " \ 141 "setenv get_cmd dhcp; " \ 142 "else " \ 143 "setenv get_cmd tftp; " \ 144 "fi; " \ 145 "${get_cmd} ${image}; " \ 146 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 147 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 148 "bootz ${loadaddr} - ${fdt_addr}; " \ 149 "else " \ 150 "if test ${boot_fdt} = try; then " \ 151 "bootz; " \ 152 "else " \ 153 "echo ERROR: Cannot load the DT; " \ 154 "exit; " \ 155 "fi; " \ 156 "fi; " \ 157 "else " \ 158 "bootz; " \ 159 "fi;\0" 160 161 #define CONFIG_BOOTCOMMAND \ 162 "mmc dev ${mmcdev}; if mmc rescan; then " \ 163 "if run loadbootscript; then " \ 164 "run bootscript; " \ 165 "else " \ 166 "if run loadimage; then " \ 167 "run mmcboot; " \ 168 "else run netboot; " \ 169 "fi; " \ 170 "fi; " \ 171 "else run netboot; fi" 172 173 #define CONFIG_ARP_TIMEOUT 200UL 174 175 /* 176 * Miscellaneous configurable options 177 */ 178 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 179 #define CONFIG_AUTO_COMPLETE 180 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 181 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 182 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 183 184 #define CONFIG_SYS_MEMTEST_START 0x90000000 185 #define CONFIG_SYS_MEMTEST_END 0x90010000 186 187 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 188 189 #define CONFIG_CMDLINE_EDITING 190 191 /*----------------------------------------------------------------------- 192 * Physical Memory Map 193 */ 194 #define CONFIG_NR_DRAM_BANKS 1 195 #define PHYS_SDRAM_1 CSD0_BASE_ADDR 196 #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) 197 198 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) 199 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) 200 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) 201 202 #define CONFIG_SYS_INIT_SP_OFFSET \ 203 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 204 #define CONFIG_SYS_INIT_SP_ADDR \ 205 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 206 207 #define CONFIG_SYS_DDR_CLKSEL 0 208 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 209 #define CONFIG_SYS_MAIN_PWR_ON 210 211 /*----------------------------------------------------------------------- 212 * environment organization 213 */ 214 #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 215 #define CONFIG_ENV_SIZE (8 * 1024) 216 #define CONFIG_ENV_IS_IN_MMC 217 #define CONFIG_SYS_MMC_ENV_DEV 0 218 219 #endif 220