1 /* 2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * (C) Copyright 2004 5 * Texas Instruments. 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Kshitij Gupta <kshitij@ti.com> 8 * 9 * Configuration settings for the Freescale i.MX31 PDK board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #include <asm/arch/imx-regs.h> 18 19 /* High Level Configuration Options */ 20 #define CONFIG_MX31 /* This is a mx31 */ 21 22 #define CONFIG_SYS_GENERIC_BOARD 23 24 #define CONFIG_DISPLAY_CPUINFO 25 #define CONFIG_DISPLAY_BOARDINFO 26 27 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 28 #define CONFIG_SETUP_MEMORY_TAGS 29 #define CONFIG_INITRD_TAG 30 31 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS 32 33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 34 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 35 #define CONFIG_SPL_MAX_SIZE 2048 36 #define CONFIG_SPL_NAND_SUPPORT 37 #define CONFIG_SPL_LIBGENERIC_SUPPORT 38 #define CONFIG_SPL_SERIAL_SUPPORT 39 40 #define CONFIG_SPL_TEXT_BASE 0x87dc0000 41 #define CONFIG_SYS_TEXT_BASE 0x87e00000 42 43 #ifndef CONFIG_SPL_BUILD 44 #define CONFIG_SKIP_LOWLEVEL_INIT 45 #endif 46 47 /* 48 * Size of malloc() pool 49 */ 50 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 51 52 /* 53 * Hardware drivers 54 */ 55 56 #define CONFIG_MXC_UART 57 #define CONFIG_MXC_UART_BASE UART1_BASE 58 #define CONFIG_MXC_GPIO 59 60 #define CONFIG_HARD_SPI 61 #define CONFIG_MXC_SPI 62 #define CONFIG_DEFAULT_SPI_BUS 1 63 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 64 65 /* PMIC Controller */ 66 #define CONFIG_POWER 67 #define CONFIG_POWER_SPI 68 #define CONFIG_POWER_FSL 69 #define CONFIG_FSL_PMIC_BUS 1 70 #define CONFIG_FSL_PMIC_CS 2 71 #define CONFIG_FSL_PMIC_CLK 1000000 72 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 73 #define CONFIG_FSL_PMIC_BITLEN 32 74 #define CONFIG_RTC_MC13XXX 75 76 /* allow to overwrite serial and ethaddr */ 77 #define CONFIG_ENV_OVERWRITE 78 #define CONFIG_CONS_INDEX 1 79 #define CONFIG_BAUDRATE 115200 80 81 /*********************************************************** 82 * Command definition 83 ***********************************************************/ 84 #define CONFIG_CMD_MII 85 #define CONFIG_CMD_PING 86 #define CONFIG_CMD_DHCP 87 #define CONFIG_CMD_SPI 88 #define CONFIG_CMD_DATE 89 #define CONFIG_CMD_NAND 90 #define CONFIG_CMD_BOOTZ 91 92 #define CONFIG_BOARD_LATE_INIT 93 94 #define CONFIG_BOOTDELAY 1 95 96 #define CONFIG_EXTRA_ENV_SETTINGS \ 97 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 98 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 99 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 100 "bootcmd=run bootcmd_net\0" \ 101 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 102 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 103 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ 104 "nand erase 0x0 0x40000; " \ 105 "nand write 0x81000000 0x0 0x40000\0" 106 107 #define CONFIG_SMC911X 108 #define CONFIG_SMC911X_BASE 0xB6000000 109 #define CONFIG_SMC911X_32_BIT 110 111 /* 112 * Miscellaneous configurable options 113 */ 114 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 115 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 116 /* max number of command args */ 117 #define CONFIG_SYS_MAXARGS 16 118 /* Boot Argument Buffer Size */ 119 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 120 121 /* memtest works on */ 122 #define CONFIG_SYS_MEMTEST_START 0x80000000 123 #define CONFIG_SYS_MEMTEST_END 0x80010000 124 125 /* default load address */ 126 #define CONFIG_SYS_LOAD_ADDR 0x81000000 127 128 #define CONFIG_CMDLINE_EDITING 129 130 /*----------------------------------------------------------------------- 131 * Physical Memory Map 132 */ 133 #define CONFIG_NR_DRAM_BANKS 1 134 #define PHYS_SDRAM_1 CSD0_BASE 135 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 136 #define CONFIG_BOARD_EARLY_INIT_F 137 138 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 139 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 140 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 141 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 142 GENERATED_GBL_DATA_SIZE) 143 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 144 CONFIG_SYS_INIT_RAM_SIZE) 145 146 /*----------------------------------------------------------------------- 147 * FLASH and environment organization 148 */ 149 /* No NOR flash present */ 150 #define CONFIG_SYS_NO_FLASH 151 152 #define CONFIG_ENV_IS_IN_NAND 153 #define CONFIG_ENV_OFFSET 0x40000 154 #define CONFIG_ENV_OFFSET_REDUND 0x60000 155 #define CONFIG_ENV_SIZE (128 * 1024) 156 157 /* 158 * NAND driver 159 */ 160 #define CONFIG_NAND_MXC 161 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 162 #define CONFIG_SYS_MAX_NAND_DEVICE 1 163 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 164 #define CONFIG_MXC_NAND_HWECC 165 #define CONFIG_SYS_NAND_LARGEPAGE 166 167 /* NAND configuration for the NAND_SPL */ 168 169 /* Start copying real U-boot from the second page */ 170 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 171 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 172 /* Load U-Boot to this address */ 173 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 174 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 175 176 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 177 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 178 #define CONFIG_SYS_NAND_PAGE_COUNT 64 179 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 180 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 181 182 183 /* Configuration of lowlevel_init.S (clocks and SDRAM) */ 184 #define CCM_CCMR_SETUP 0x074B0BF5 185 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ 186 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ 187 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ 188 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) 189 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 190 PLL_MFN(12)) 191 192 #define ESDMISC_MDDR_SETUP 0x00000004 193 #define ESDMISC_MDDR_RESET_DL 0x0000000c 194 #define ESDCFG0_MDDR_SETUP 0x006ac73a 195 196 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 197 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 198 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 199 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 200 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 201 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 202 #define ESDCTL_RW ESDCTL_SETTINGS 203 204 #endif /* __CONFIG_H */ 205