1 /* 2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * (C) Copyright 2004 5 * Texas Instruments. 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Kshitij Gupta <kshitij@ti.com> 8 * 9 * Configuration settings for the Freescale i.MX31 PDK board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #include <asm/arch/imx-regs.h> 18 19 /* High Level Configuration Options */ 20 #define CONFIG_MX31 /* This is a mx31 */ 21 22 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 23 #define CONFIG_SETUP_MEMORY_TAGS 24 #define CONFIG_INITRD_TAG 25 26 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS 27 28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 29 #define CONFIG_SPL_MAX_SIZE 2048 30 31 #define CONFIG_SPL_TEXT_BASE 0x87dc0000 32 33 #ifndef CONFIG_SPL_BUILD 34 #define CONFIG_SKIP_LOWLEVEL_INIT 35 #endif 36 37 /* 38 * Size of malloc() pool 39 */ 40 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 41 42 /* 43 * Hardware drivers 44 */ 45 46 #define CONFIG_MXC_UART 47 #define CONFIG_MXC_UART_BASE UART1_BASE 48 49 #define CONFIG_HARD_SPI 50 #define CONFIG_DEFAULT_SPI_BUS 1 51 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 52 53 /* PMIC Controller */ 54 #define CONFIG_POWER 55 #define CONFIG_POWER_SPI 56 #define CONFIG_POWER_FSL 57 #define CONFIG_FSL_PMIC_BUS 1 58 #define CONFIG_FSL_PMIC_CS 2 59 #define CONFIG_FSL_PMIC_CLK 1000000 60 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 61 #define CONFIG_FSL_PMIC_BITLEN 32 62 #define CONFIG_RTC_MC13XXX 63 64 /* allow to overwrite serial and ethaddr */ 65 #define CONFIG_ENV_OVERWRITE 66 67 #define CONFIG_EXTRA_ENV_SETTINGS \ 68 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 69 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 70 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 71 "bootcmd=run bootcmd_net\0" \ 72 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 73 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 74 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ 75 "nand erase 0x0 0x40000; " \ 76 "nand write 0x81000000 0x0 0x40000\0" 77 78 /* 79 * Miscellaneous configurable options 80 */ 81 82 /* memtest works on */ 83 #define CONFIG_SYS_MEMTEST_START 0x80000000 84 #define CONFIG_SYS_MEMTEST_END 0x80010000 85 86 /* default load address */ 87 #define CONFIG_SYS_LOAD_ADDR 0x81000000 88 89 /*----------------------------------------------------------------------- 90 * Physical Memory Map 91 */ 92 #define CONFIG_NR_DRAM_BANKS 1 93 #define PHYS_SDRAM_1 CSD0_BASE 94 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 95 96 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 97 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 98 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 99 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 100 GENERATED_GBL_DATA_SIZE) 101 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 102 CONFIG_SYS_INIT_RAM_SIZE) 103 104 /* 105 * environment organization 106 */ 107 #define CONFIG_ENV_OFFSET 0x40000 108 #define CONFIG_ENV_OFFSET_REDUND 0x60000 109 #define CONFIG_ENV_SIZE (128 * 1024) 110 111 /* 112 * NAND driver 113 */ 114 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 115 #define CONFIG_SYS_MAX_NAND_DEVICE 1 116 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 117 #define CONFIG_MXC_NAND_HWECC 118 #define CONFIG_SYS_NAND_LARGEPAGE 119 120 /* NAND configuration for the NAND_SPL */ 121 122 /* Start copying real U-Boot from the second page */ 123 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 124 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 125 /* Load U-Boot to this address */ 126 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 127 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 128 129 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 130 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 131 #define CONFIG_SYS_NAND_PAGE_COUNT 64 132 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 133 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 134 135 /* Configuration of lowlevel_init.S (clocks and SDRAM) */ 136 #define CCM_CCMR_SETUP 0x074B0BF5 137 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ 138 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ 139 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ 140 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) 141 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 142 PLL_MFN(12)) 143 144 #define ESDMISC_MDDR_SETUP 0x00000004 145 #define ESDMISC_MDDR_RESET_DL 0x0000000c 146 #define ESDCFG0_MDDR_SETUP 0x006ac73a 147 148 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 149 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 150 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 151 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 152 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 153 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 154 #define ESDCTL_RW ESDCTL_SETTINGS 155 156 #endif /* __CONFIG_H */ 157