1 /* 2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * (C) Copyright 2004 5 * Texas Instruments. 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Kshitij Gupta <kshitij@ti.com> 8 * 9 * Configuration settings for the Freescale i.MX31 PDK board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #include <asm/arch/imx-regs.h> 18 19 /* High Level Configuration Options */ 20 #define CONFIG_MX31 /* This is a mx31 */ 21 22 #define CONFIG_DISPLAY_CPUINFO 23 #define CONFIG_DISPLAY_BOARDINFO 24 25 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 26 #define CONFIG_SETUP_MEMORY_TAGS 27 #define CONFIG_INITRD_TAG 28 29 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS 30 31 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 32 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 33 #define CONFIG_SPL_MAX_SIZE 2048 34 35 #define CONFIG_SPL_TEXT_BASE 0x87dc0000 36 #define CONFIG_SYS_TEXT_BASE 0x87e00000 37 38 #ifndef CONFIG_SPL_BUILD 39 #define CONFIG_SKIP_LOWLEVEL_INIT 40 #endif 41 42 /* 43 * Size of malloc() pool 44 */ 45 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 46 47 /* 48 * Hardware drivers 49 */ 50 51 #define CONFIG_MXC_UART 52 #define CONFIG_MXC_UART_BASE UART1_BASE 53 #define CONFIG_MXC_GPIO 54 55 #define CONFIG_HARD_SPI 56 #define CONFIG_MXC_SPI 57 #define CONFIG_DEFAULT_SPI_BUS 1 58 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 59 60 /* PMIC Controller */ 61 #define CONFIG_POWER 62 #define CONFIG_POWER_SPI 63 #define CONFIG_POWER_FSL 64 #define CONFIG_FSL_PMIC_BUS 1 65 #define CONFIG_FSL_PMIC_CS 2 66 #define CONFIG_FSL_PMIC_CLK 1000000 67 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 68 #define CONFIG_FSL_PMIC_BITLEN 32 69 #define CONFIG_RTC_MC13XXX 70 71 /* allow to overwrite serial and ethaddr */ 72 #define CONFIG_ENV_OVERWRITE 73 #define CONFIG_CONS_INDEX 1 74 #define CONFIG_BAUDRATE 115200 75 76 /*********************************************************** 77 * Command definition 78 ***********************************************************/ 79 #define CONFIG_CMD_DATE 80 #define CONFIG_CMD_NAND 81 82 #define CONFIG_BOARD_LATE_INIT 83 84 85 #define CONFIG_EXTRA_ENV_SETTINGS \ 86 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 87 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 88 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 89 "bootcmd=run bootcmd_net\0" \ 90 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 91 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 92 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ 93 "nand erase 0x0 0x40000; " \ 94 "nand write 0x81000000 0x0 0x40000\0" 95 96 #define CONFIG_SMC911X 97 #define CONFIG_SMC911X_BASE 0xB6000000 98 #define CONFIG_SMC911X_32_BIT 99 100 /* 101 * Miscellaneous configurable options 102 */ 103 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 104 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 105 /* max number of command args */ 106 #define CONFIG_SYS_MAXARGS 16 107 /* Boot Argument Buffer Size */ 108 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 109 110 /* memtest works on */ 111 #define CONFIG_SYS_MEMTEST_START 0x80000000 112 #define CONFIG_SYS_MEMTEST_END 0x80010000 113 114 /* default load address */ 115 #define CONFIG_SYS_LOAD_ADDR 0x81000000 116 117 #define CONFIG_CMDLINE_EDITING 118 119 /*----------------------------------------------------------------------- 120 * Physical Memory Map 121 */ 122 #define CONFIG_NR_DRAM_BANKS 1 123 #define PHYS_SDRAM_1 CSD0_BASE 124 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 125 #define CONFIG_BOARD_EARLY_INIT_F 126 127 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 128 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 129 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 130 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 131 GENERATED_GBL_DATA_SIZE) 132 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 133 CONFIG_SYS_INIT_RAM_SIZE) 134 135 /*----------------------------------------------------------------------- 136 * FLASH and environment organization 137 */ 138 /* No NOR flash present */ 139 #define CONFIG_SYS_NO_FLASH 140 141 #define CONFIG_ENV_IS_IN_NAND 142 #define CONFIG_ENV_OFFSET 0x40000 143 #define CONFIG_ENV_OFFSET_REDUND 0x60000 144 #define CONFIG_ENV_SIZE (128 * 1024) 145 146 /* 147 * NAND driver 148 */ 149 #define CONFIG_NAND_MXC 150 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 151 #define CONFIG_SYS_MAX_NAND_DEVICE 1 152 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 153 #define CONFIG_MXC_NAND_HWECC 154 #define CONFIG_SYS_NAND_LARGEPAGE 155 156 /* NAND configuration for the NAND_SPL */ 157 158 /* Start copying real U-Boot from the second page */ 159 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 160 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 161 /* Load U-Boot to this address */ 162 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 163 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 164 165 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 166 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 167 #define CONFIG_SYS_NAND_PAGE_COUNT 64 168 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 169 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 170 171 /* Configuration of lowlevel_init.S (clocks and SDRAM) */ 172 #define CCM_CCMR_SETUP 0x074B0BF5 173 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ 174 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ 175 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ 176 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) 177 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 178 PLL_MFN(12)) 179 180 #define ESDMISC_MDDR_SETUP 0x00000004 181 #define ESDMISC_MDDR_RESET_DL 0x0000000c 182 #define ESDCFG0_MDDR_SETUP 0x006ac73a 183 184 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 185 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 186 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 187 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 188 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 189 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 190 #define ESDCTL_RW ESDCTL_SETTINGS 191 192 #endif /* __CONFIG_H */ 193