1 /* 2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * (C) Copyright 2004 5 * Texas Instruments. 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Kshitij Gupta <kshitij@ti.com> 8 * 9 * Configuration settings for the Freescale i.MX31 PDK board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #include <asm/arch/imx-regs.h> 18 19 /* High Level Configuration Options */ 20 #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ 21 #define CONFIG_MX31 /* in a mx31 */ 22 23 #define CONFIG_DISPLAY_CPUINFO 24 #define CONFIG_DISPLAY_BOARDINFO 25 26 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 27 #define CONFIG_SETUP_MEMORY_TAGS 28 #define CONFIG_INITRD_TAG 29 30 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS 31 32 #define CONFIG_SPL 33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 34 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 35 #define CONFIG_SPL_MAX_SIZE 2048 36 #define CONFIG_SPL_NAND_SUPPORT 37 #define CONFIG_SPL_LIBGENERIC_SUPPORT 38 39 #define CONFIG_SPL_TEXT_BASE 0x87dc0000 40 #define CONFIG_SYS_TEXT_BASE 0x87e00000 41 42 #ifndef CONFIG_SPL_BUILD 43 #define CONFIG_SKIP_LOWLEVEL_INIT 44 #endif 45 46 /* 47 * Size of malloc() pool 48 */ 49 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 50 51 /* 52 * Hardware drivers 53 */ 54 55 #define CONFIG_MXC_UART 56 #define CONFIG_MXC_UART_BASE UART1_BASE 57 #define CONFIG_MXC_GPIO 58 59 #define CONFIG_HARD_SPI 60 #define CONFIG_MXC_SPI 61 #define CONFIG_DEFAULT_SPI_BUS 1 62 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 63 64 /* PMIC Controller */ 65 #define CONFIG_POWER 66 #define CONFIG_POWER_SPI 67 #define CONFIG_POWER_FSL 68 #define CONFIG_FSL_PMIC_BUS 1 69 #define CONFIG_FSL_PMIC_CS 2 70 #define CONFIG_FSL_PMIC_CLK 1000000 71 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 72 #define CONFIG_FSL_PMIC_BITLEN 32 73 #define CONFIG_RTC_MC13XXX 74 75 /* allow to overwrite serial and ethaddr */ 76 #define CONFIG_ENV_OVERWRITE 77 #define CONFIG_CONS_INDEX 1 78 #define CONFIG_BAUDRATE 115200 79 80 /*********************************************************** 81 * Command definition 82 ***********************************************************/ 83 84 #include <config_cmd_default.h> 85 86 #define CONFIG_CMD_MII 87 #define CONFIG_CMD_PING 88 #define CONFIG_CMD_DHCP 89 #define CONFIG_CMD_SPI 90 #define CONFIG_CMD_DATE 91 #define CONFIG_CMD_NAND 92 #define CONFIG_CMD_BOOTZ 93 94 /* 95 * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require 96 * that CFG_NO_FLASH is undefined). 97 */ 98 #undef CONFIG_CMD_IMLS 99 100 #define CONFIG_BOARD_LATE_INIT 101 102 #define CONFIG_BOOTDELAY 1 103 104 #define CONFIG_EXTRA_ENV_SETTINGS \ 105 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 106 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 107 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 108 "bootcmd=run bootcmd_net\0" \ 109 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 110 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 111 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ 112 "nand erase 0x0 0x40000; " \ 113 "nand write 0x81000000 0x0 0x40000\0" 114 115 #define CONFIG_SMC911X 116 #define CONFIG_SMC911X_BASE 0xB6000000 117 #define CONFIG_SMC911X_32_BIT 118 119 /* 120 * Miscellaneous configurable options 121 */ 122 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 123 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 124 /* Print Buffer Size */ 125 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 126 sizeof(CONFIG_SYS_PROMPT)+16) 127 /* max number of command args */ 128 #define CONFIG_SYS_MAXARGS 16 129 /* Boot Argument Buffer Size */ 130 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 131 132 /* memtest works on */ 133 #define CONFIG_SYS_MEMTEST_START 0x80000000 134 #define CONFIG_SYS_MEMTEST_END 0x80010000 135 136 /* default load address */ 137 #define CONFIG_SYS_LOAD_ADDR 0x81000000 138 139 #define CONFIG_CMDLINE_EDITING 140 141 /*----------------------------------------------------------------------- 142 * Physical Memory Map 143 */ 144 #define CONFIG_NR_DRAM_BANKS 1 145 #define PHYS_SDRAM_1 CSD0_BASE 146 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 147 #define CONFIG_BOARD_EARLY_INIT_F 148 149 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 150 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 151 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 152 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 153 GENERATED_GBL_DATA_SIZE) 154 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 155 CONFIG_SYS_INIT_RAM_SIZE) 156 157 /*----------------------------------------------------------------------- 158 * FLASH and environment organization 159 */ 160 /* No NOR flash present */ 161 #define CONFIG_SYS_NO_FLASH 162 163 #define CONFIG_ENV_IS_IN_NAND 164 #define CONFIG_ENV_OFFSET 0x40000 165 #define CONFIG_ENV_OFFSET_REDUND 0x60000 166 #define CONFIG_ENV_SIZE (128 * 1024) 167 168 /* 169 * NAND driver 170 */ 171 #define CONFIG_NAND_MXC 172 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 173 #define CONFIG_SYS_MAX_NAND_DEVICE 1 174 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 175 #define CONFIG_MXC_NAND_HWECC 176 #define CONFIG_SYS_NAND_LARGEPAGE 177 178 /* NAND configuration for the NAND_SPL */ 179 180 /* Start copying real U-boot from the second page */ 181 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 182 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 183 /* Load U-Boot to this address */ 184 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 185 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 186 187 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 188 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 189 #define CONFIG_SYS_NAND_PAGE_COUNT 64 190 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 191 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 192 193 194 /* Configuration of lowlevel_init.S (clocks and SDRAM) */ 195 #define CCM_CCMR_SETUP 0x074B0BF5 196 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ 197 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ 198 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ 199 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) 200 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 201 PLL_MFN(12)) 202 203 #define ESDMISC_MDDR_SETUP 0x00000004 204 #define ESDMISC_MDDR_RESET_DL 0x0000000c 205 #define ESDCFG0_MDDR_SETUP 0x006ac73a 206 207 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 208 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 209 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 210 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 211 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 212 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 213 #define ESDCTL_RW ESDCTL_SETTINGS 214 215 #endif /* __CONFIG_H */ 216