1 /* 2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * (C) Copyright 2004 5 * Texas Instruments. 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Kshitij Gupta <kshitij@ti.com> 8 * 9 * Configuration settings for the Freescale i.MX31 PDK board. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 #ifndef __CONFIG_H 31 #define __CONFIG_H 32 33 #include <asm/arch/imx-regs.h> 34 35 /* High Level Configuration Options */ 36 #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ 37 #define CONFIG_MX31 /* in a mx31 */ 38 #define CONFIG_MX31_HCLK_FREQ 26000000 39 #define CONFIG_MX31_CLK32 32768 40 41 #define CONFIG_DISPLAY_CPUINFO 42 #define CONFIG_DISPLAY_BOARDINFO 43 44 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 45 #define CONFIG_SETUP_MEMORY_TAGS 46 #define CONFIG_INITRD_TAG 47 48 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS 49 50 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 51 #define CONFIG_SKIP_LOWLEVEL_INIT 52 #endif 53 54 /* 55 * Size of malloc() pool 56 */ 57 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 58 59 /* 60 * Hardware drivers 61 */ 62 63 #define CONFIG_MXC_UART 64 #define CONFIG_MXC_UART_BASE UART1_BASE 65 #define CONFIG_HW_WATCHDOG 66 #define CONFIG_MXC_GPIO 67 68 #define CONFIG_HARD_SPI 69 #define CONFIG_MXC_SPI 70 #define CONFIG_DEFAULT_SPI_BUS 1 71 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 72 73 /* PMIC Controller */ 74 #define CONFIG_PMIC 75 #define CONFIG_PMIC_SPI 76 #define CONFIG_PMIC_FSL 77 #define CONFIG_FSL_PMIC_BUS 1 78 #define CONFIG_FSL_PMIC_CS 2 79 #define CONFIG_FSL_PMIC_CLK 1000000 80 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 81 #define CONFIG_FSL_PMIC_BITLEN 32 82 #define CONFIG_RTC_MC13XXX 83 84 /* allow to overwrite serial and ethaddr */ 85 #define CONFIG_ENV_OVERWRITE 86 #define CONFIG_CONS_INDEX 1 87 #define CONFIG_BAUDRATE 115200 88 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} 89 90 /*********************************************************** 91 * Command definition 92 ***********************************************************/ 93 94 #include <config_cmd_default.h> 95 96 #define CONFIG_CMD_MII 97 #define CONFIG_CMD_PING 98 #define CONFIG_CMD_DHCP 99 #define CONFIG_CMD_SPI 100 #define CONFIG_CMD_DATE 101 #define CONFIG_CMD_NAND 102 103 /* 104 * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require 105 * that CFG_NO_FLASH is undefined). 106 */ 107 #undef CONFIG_CMD_IMLS 108 109 #define CONFIG_BOARD_LATE_INIT 110 111 #define CONFIG_BOOTDELAY 3 112 113 #define CONFIG_EXTRA_ENV_SETTINGS \ 114 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 115 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 116 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 117 "bootcmd=run bootcmd_net\0" \ 118 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 119 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 120 "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \ 121 "nand erase 0x0 0x40000; " \ 122 "nand write 0x81000000 0x0 0x40000\0" 123 124 #define CONFIG_SMC911X 125 #define CONFIG_SMC911X_BASE 0xB6000000 126 #define CONFIG_SMC911X_32_BIT 127 128 /* 129 * Miscellaneous configurable options 130 */ 131 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 132 #define CONFIG_SYS_PROMPT "MX31PDK U-Boot > " 133 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 134 /* Print Buffer Size */ 135 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 136 sizeof(CONFIG_SYS_PROMPT)+16) 137 /* max number of command args */ 138 #define CONFIG_SYS_MAXARGS 16 139 /* Boot Argument Buffer Size */ 140 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 141 142 /* memtest works on */ 143 #define CONFIG_SYS_MEMTEST_START 0x80000000 144 #define CONFIG_SYS_MEMTEST_END 0x10000 145 146 /* default load address */ 147 #define CONFIG_SYS_LOAD_ADDR 0x81000000 148 149 #define CONFIG_SYS_HZ 1000 150 151 #define CONFIG_CMDLINE_EDITING 152 153 /*----------------------------------------------------------------------- 154 * Stack sizes 155 * 156 * The stack sizes are set up in start.S using the settings below 157 */ 158 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ 159 160 /*----------------------------------------------------------------------- 161 * Physical Memory Map 162 */ 163 #define CONFIG_NR_DRAM_BANKS 1 164 #define PHYS_SDRAM_1 CSD0_BASE 165 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 166 #define CONFIG_BOARD_EARLY_INIT_F 167 168 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 169 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 170 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 171 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 172 GENERATED_GBL_DATA_SIZE) 173 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 174 CONFIG_SYS_GBL_DATA_OFFSET) 175 176 /*----------------------------------------------------------------------- 177 * FLASH and environment organization 178 */ 179 /* No NOR flash present */ 180 #define CONFIG_SYS_NO_FLASH 181 182 #define CONFIG_ENV_IS_IN_NAND 183 #define CONFIG_ENV_OFFSET 0x40000 184 #define CONFIG_ENV_OFFSET_REDUND 0x60000 185 #define CONFIG_ENV_SIZE (128 * 1024) 186 187 /* 188 * NAND driver 189 */ 190 #define CONFIG_NAND_MXC 191 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 192 #define CONFIG_SYS_MAX_NAND_DEVICE 1 193 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 194 #define CONFIG_MXC_NAND_HWECC 195 #define CONFIG_SYS_NAND_LARGEPAGE 196 197 /* NAND configuration for the NAND_SPL */ 198 199 /* Start copying real U-boot from the second page */ 200 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 201 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 202 /* Load U-Boot to this address */ 203 #define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000 204 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 205 206 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 207 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 208 #define CONFIG_SYS_NAND_PAGE_COUNT 64 209 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 210 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 211 212 213 /* Configuration of lowlevel_init.S (clocks and SDRAM) */ 214 #define CCM_CCMR_SETUP 0x074B0BF5 215 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \ 216 PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \ 217 PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \ 218 PDR0_MCU_PODF(0)) 219 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 220 PLL_MFN(12)) 221 222 #define ESDMISC_MDDR_SETUP 0x00000004 223 #define ESDMISC_MDDR_RESET_DL 0x0000000c 224 #define ESDCFG0_MDDR_SETUP 0x006ac73a 225 226 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 227 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 228 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 229 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 230 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 231 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 232 #define ESDCTL_RW ESDCTL_SETTINGS 233 234 #endif /* __CONFIG_H */ 235