1 /* 2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * (C) Copyright 2004 5 * Texas Instruments. 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Kshitij Gupta <kshitij@ti.com> 8 * 9 * Configuration settings for the Freescale i.MX31 PDK board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #include <asm/arch/imx-regs.h> 18 19 /* High Level Configuration Options */ 20 #define CONFIG_MX31 /* This is a mx31 */ 21 22 23 #define CONFIG_DISPLAY_CPUINFO 24 #define CONFIG_DISPLAY_BOARDINFO 25 26 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 27 #define CONFIG_SETUP_MEMORY_TAGS 28 #define CONFIG_INITRD_TAG 29 30 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS 31 32 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 33 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 34 #define CONFIG_SPL_MAX_SIZE 2048 35 #define CONFIG_SPL_NAND_SUPPORT 36 #define CONFIG_SPL_LIBGENERIC_SUPPORT 37 #define CONFIG_SPL_SERIAL_SUPPORT 38 39 #define CONFIG_SPL_TEXT_BASE 0x87dc0000 40 #define CONFIG_SYS_TEXT_BASE 0x87e00000 41 42 #ifndef CONFIG_SPL_BUILD 43 #define CONFIG_SKIP_LOWLEVEL_INIT 44 #endif 45 46 /* 47 * Size of malloc() pool 48 */ 49 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 50 51 /* 52 * Hardware drivers 53 */ 54 55 #define CONFIG_MXC_UART 56 #define CONFIG_MXC_UART_BASE UART1_BASE 57 #define CONFIG_MXC_GPIO 58 59 #define CONFIG_HARD_SPI 60 #define CONFIG_MXC_SPI 61 #define CONFIG_DEFAULT_SPI_BUS 1 62 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 63 64 /* PMIC Controller */ 65 #define CONFIG_POWER 66 #define CONFIG_POWER_SPI 67 #define CONFIG_POWER_FSL 68 #define CONFIG_FSL_PMIC_BUS 1 69 #define CONFIG_FSL_PMIC_CS 2 70 #define CONFIG_FSL_PMIC_CLK 1000000 71 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 72 #define CONFIG_FSL_PMIC_BITLEN 32 73 #define CONFIG_RTC_MC13XXX 74 75 /* allow to overwrite serial and ethaddr */ 76 #define CONFIG_ENV_OVERWRITE 77 #define CONFIG_CONS_INDEX 1 78 #define CONFIG_BAUDRATE 115200 79 80 /*********************************************************** 81 * Command definition 82 ***********************************************************/ 83 #define CONFIG_CMD_MII 84 #define CONFIG_CMD_PING 85 #define CONFIG_CMD_DHCP 86 #define CONFIG_CMD_SPI 87 #define CONFIG_CMD_DATE 88 #define CONFIG_CMD_NAND 89 #define CONFIG_CMD_BOOTZ 90 91 #define CONFIG_BOARD_LATE_INIT 92 93 #define CONFIG_BOOTDELAY 1 94 95 #define CONFIG_EXTRA_ENV_SETTINGS \ 96 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 97 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 98 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 99 "bootcmd=run bootcmd_net\0" \ 100 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 101 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 102 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ 103 "nand erase 0x0 0x40000; " \ 104 "nand write 0x81000000 0x0 0x40000\0" 105 106 #define CONFIG_SMC911X 107 #define CONFIG_SMC911X_BASE 0xB6000000 108 #define CONFIG_SMC911X_32_BIT 109 110 /* 111 * Miscellaneous configurable options 112 */ 113 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 114 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 115 /* max number of command args */ 116 #define CONFIG_SYS_MAXARGS 16 117 /* Boot Argument Buffer Size */ 118 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 119 120 /* memtest works on */ 121 #define CONFIG_SYS_MEMTEST_START 0x80000000 122 #define CONFIG_SYS_MEMTEST_END 0x80010000 123 124 /* default load address */ 125 #define CONFIG_SYS_LOAD_ADDR 0x81000000 126 127 #define CONFIG_CMDLINE_EDITING 128 129 /*----------------------------------------------------------------------- 130 * Physical Memory Map 131 */ 132 #define CONFIG_NR_DRAM_BANKS 1 133 #define PHYS_SDRAM_1 CSD0_BASE 134 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 135 #define CONFIG_BOARD_EARLY_INIT_F 136 137 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 138 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 139 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 140 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 141 GENERATED_GBL_DATA_SIZE) 142 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 143 CONFIG_SYS_INIT_RAM_SIZE) 144 145 /*----------------------------------------------------------------------- 146 * FLASH and environment organization 147 */ 148 /* No NOR flash present */ 149 #define CONFIG_SYS_NO_FLASH 150 151 #define CONFIG_ENV_IS_IN_NAND 152 #define CONFIG_ENV_OFFSET 0x40000 153 #define CONFIG_ENV_OFFSET_REDUND 0x60000 154 #define CONFIG_ENV_SIZE (128 * 1024) 155 156 /* 157 * NAND driver 158 */ 159 #define CONFIG_NAND_MXC 160 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 161 #define CONFIG_SYS_MAX_NAND_DEVICE 1 162 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 163 #define CONFIG_MXC_NAND_HWECC 164 #define CONFIG_SYS_NAND_LARGEPAGE 165 166 /* NAND configuration for the NAND_SPL */ 167 168 /* Start copying real U-Boot from the second page */ 169 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 170 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 171 /* Load U-Boot to this address */ 172 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 173 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 174 175 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 176 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 177 #define CONFIG_SYS_NAND_PAGE_COUNT 64 178 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 179 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 180 181 182 /* Configuration of lowlevel_init.S (clocks and SDRAM) */ 183 #define CCM_CCMR_SETUP 0x074B0BF5 184 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ 185 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ 186 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ 187 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) 188 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 189 PLL_MFN(12)) 190 191 #define ESDMISC_MDDR_SETUP 0x00000004 192 #define ESDMISC_MDDR_RESET_DL 0x0000000c 193 #define ESDCFG0_MDDR_SETUP 0x006ac73a 194 195 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 196 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 197 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 198 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 199 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 200 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 201 #define ESDCTL_RW ESDCTL_SETTINGS 202 203 #endif /* __CONFIG_H */ 204