1 /* 2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * (C) Copyright 2004 5 * Texas Instruments. 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Kshitij Gupta <kshitij@ti.com> 8 * 9 * Configuration settings for the Freescale i.MX31 PDK board. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 #ifndef __CONFIG_H 31 #define __CONFIG_H 32 33 #include <asm/arch/mx31-regs.h> 34 35 /* High Level Configuration Options */ 36 #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ 37 #define CONFIG_MX31 1 /* in a mx31 */ 38 #define CONFIG_MX31_HCLK_FREQ 26000000 39 #define CONFIG_MX31_CLK32 32768 40 41 #define CONFIG_DISPLAY_CPUINFO 42 #define CONFIG_DISPLAY_BOARDINFO 43 44 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 45 #define CONFIG_SETUP_MEMORY_TAGS 1 46 #define CONFIG_INITRD_TAG 1 47 48 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 49 #define CONFIG_SKIP_LOWLEVEL_INIT 50 #define CONFIG_SKIP_RELOCATE_UBOOT 51 #endif 52 53 /* 54 * Size of malloc() pool 55 */ 56 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 57 /* Bytes reserved for initial data */ 58 #define CONFIG_SYS_GBL_DATA_SIZE 128 59 60 /* 61 * Hardware drivers 62 */ 63 64 #define CONFIG_MXC_UART 1 65 #define CONFIG_SYS_MX31_UART1 1 66 67 #define CONFIG_HARD_SPI 1 68 #define CONFIG_MXC_SPI 1 69 #define CONFIG_DEFAULT_SPI_BUS 1 70 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) 71 72 #define CONFIG_FSL_PMIC 73 #define CONFIG_FSL_PMIC_BUS 1 74 #define CONFIG_FSL_PMIC_CS 2 75 #define CONFIG_FSL_PMIC_CLK 1000000 76 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) 77 #define CONFIG_RTC_MC13783 1 78 79 /* allow to overwrite serial and ethaddr */ 80 #define CONFIG_ENV_OVERWRITE 81 #define CONFIG_CONS_INDEX 1 82 #define CONFIG_BAUDRATE 115200 83 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} 84 85 /*********************************************************** 86 * Command definition 87 ***********************************************************/ 88 89 #include <config_cmd_default.h> 90 91 #define CONFIG_CMD_MII 92 #define CONFIG_CMD_PING 93 #define CONFIG_CMD_SPI 94 #define CONFIG_CMD_DATE 95 #define CONFIG_CMD_NAND 96 97 /* 98 * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require 99 * that CFG_NO_FLASH is undefined). 100 */ 101 #undef CONFIG_CMD_IMLS 102 103 #define CONFIG_BOOTDELAY 3 104 105 #define CONFIG_EXTRA_ENV_SETTINGS \ 106 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 107 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 108 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 109 "bootcmd=run bootcmd_net\0" \ 110 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 111 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 112 "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \ 113 "nand erase 0x0 0x40000; " \ 114 "nand write 0x81000000 0x0 0x40000\0" 115 116 #define CONFIG_NET_MULTI 117 #define CONFIG_SMC911X 1 118 #define CONFIG_SMC911X_BASE 0xB6000000 119 #define CONFIG_SMC911X_32_BIT 1 120 121 /* 122 * Miscellaneous configurable options 123 */ 124 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 125 #define CONFIG_SYS_PROMPT "uboot> " 126 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 127 /* Print Buffer Size */ 128 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 129 sizeof(CONFIG_SYS_PROMPT)+16) 130 /* max number of command args */ 131 #define CONFIG_SYS_MAXARGS 16 132 /* Boot Argument Buffer Size */ 133 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 134 135 /* memtest works on */ 136 #define CONFIG_SYS_MEMTEST_START 0x80000000 137 #define CONFIG_SYS_MEMTEST_END 0x10000 138 139 /* default load address */ 140 #define CONFIG_SYS_LOAD_ADDR 0x81000000 141 142 #define CONFIG_SYS_HZ 1000 143 144 #define CONFIG_CMDLINE_EDITING 1 145 146 /*----------------------------------------------------------------------- 147 * Stack sizes 148 * 149 * The stack sizes are set up in start.S using the settings below 150 */ 151 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ 152 153 /*----------------------------------------------------------------------- 154 * Physical Memory Map 155 */ 156 #define CONFIG_NR_DRAM_BANKS 1 157 #define PHYS_SDRAM_1 CSD0_BASE 158 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 159 160 /*----------------------------------------------------------------------- 161 * FLASH and environment organization 162 */ 163 /* No NOR flash present */ 164 #define CONFIG_SYS_NO_FLASH 1 165 166 #define CONFIG_ENV_IS_IN_NAND 1 167 #define CONFIG_ENV_OFFSET 0x40000 168 #define CONFIG_ENV_OFFSET_REDUND 0x60000 169 #define CONFIG_ENV_SIZE (128 * 1024) 170 171 /* 172 * NAND driver 173 */ 174 #define CONFIG_NAND_MXC 175 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 176 #define CONFIG_SYS_MAX_NAND_DEVICE 1 177 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 178 #define CONFIG_MXC_NAND_HWECC 179 #define CONFIG_SYS_NAND_LARGEPAGE 180 181 /* NAND configuration for the NAND_SPL */ 182 183 /* Start copying real U-boot from the second page */ 184 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 185 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 186 /* Load U-Boot to this address */ 187 #define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000 188 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 189 190 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 191 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 192 #define CONFIG_SYS_NAND_PAGE_COUNT 64 193 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 194 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 195 196 197 /* Configuration of lowlevel_init.S (clocks and SDRAM) */ 198 #define CCM_CCMR_SETUP 0x074B0BF5 199 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \ 200 PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \ 201 PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \ 202 PDR0_MCU_PODF(0)) 203 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 204 PLL_MFN(12)) 205 206 #define ESDMISC_MDDR_SETUP 0x00000004 207 #define ESDMISC_MDDR_RESET_DL 0x0000000c 208 #define ESDCFG0_MDDR_SETUP 0x006ac73a 209 210 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 211 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 212 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 213 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 214 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 215 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 216 #define ESDCTL_RW ESDCTL_SETTINGS 217 218 #endif /* __CONFIG_H */ 219