1 /* 2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * (C) Copyright 2004 5 * Texas Instruments. 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Kshitij Gupta <kshitij@ti.com> 8 * 9 * Configuration settings for the Freescale i.MX31 PDK board. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 #ifndef __CONFIG_H 31 #define __CONFIG_H 32 33 #include <asm/arch/imx-regs.h> 34 35 /* High Level Configuration Options */ 36 #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ 37 #define CONFIG_MX31 1 /* in a mx31 */ 38 #define CONFIG_MX31_HCLK_FREQ 26000000 39 #define CONFIG_MX31_CLK32 32768 40 41 #define CONFIG_DISPLAY_CPUINFO 42 #define CONFIG_DISPLAY_BOARDINFO 43 44 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 45 #define CONFIG_SETUP_MEMORY_TAGS 1 46 #define CONFIG_INITRD_TAG 1 47 48 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 49 #define CONFIG_SKIP_LOWLEVEL_INIT 50 #endif 51 52 /* 53 * Size of malloc() pool 54 */ 55 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 56 /* Bytes reserved for initial data */ 57 58 /* 59 * Hardware drivers 60 */ 61 62 #define CONFIG_MXC_UART 1 63 #define CONFIG_SYS_MX31_UART1 1 64 65 #define CONFIG_HARD_SPI 1 66 #define CONFIG_MXC_SPI 1 67 #define CONFIG_DEFAULT_SPI_BUS 1 68 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 69 70 #define CONFIG_FSL_PMIC 71 #define CONFIG_FSL_PMIC_BUS 1 72 #define CONFIG_FSL_PMIC_CS 2 73 #define CONFIG_FSL_PMIC_CLK 1000000 74 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 75 #define CONFIG_RTC_MC13783 1 76 77 /* allow to overwrite serial and ethaddr */ 78 #define CONFIG_ENV_OVERWRITE 79 #define CONFIG_CONS_INDEX 1 80 #define CONFIG_BAUDRATE 115200 81 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} 82 83 /*********************************************************** 84 * Command definition 85 ***********************************************************/ 86 87 #include <config_cmd_default.h> 88 89 #define CONFIG_CMD_MII 90 #define CONFIG_CMD_PING 91 #define CONFIG_CMD_SPI 92 #define CONFIG_CMD_DATE 93 #define CONFIG_CMD_NAND 94 95 /* 96 * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require 97 * that CFG_NO_FLASH is undefined). 98 */ 99 #undef CONFIG_CMD_IMLS 100 101 #define CONFIG_BOOTDELAY 3 102 103 #define CONFIG_EXTRA_ENV_SETTINGS \ 104 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 105 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 106 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 107 "bootcmd=run bootcmd_net\0" \ 108 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 109 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 110 "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \ 111 "nand erase 0x0 0x40000; " \ 112 "nand write 0x81000000 0x0 0x40000\0" 113 114 #define CONFIG_NET_MULTI 115 #define CONFIG_SMC911X 1 116 #define CONFIG_SMC911X_BASE 0xB6000000 117 #define CONFIG_SMC911X_32_BIT 1 118 119 /* 120 * Miscellaneous configurable options 121 */ 122 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 123 #define CONFIG_SYS_PROMPT "uboot> " 124 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 125 /* Print Buffer Size */ 126 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 127 sizeof(CONFIG_SYS_PROMPT)+16) 128 /* max number of command args */ 129 #define CONFIG_SYS_MAXARGS 16 130 /* Boot Argument Buffer Size */ 131 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 132 133 /* memtest works on */ 134 #define CONFIG_SYS_MEMTEST_START 0x80000000 135 #define CONFIG_SYS_MEMTEST_END 0x10000 136 137 /* default load address */ 138 #define CONFIG_SYS_LOAD_ADDR 0x81000000 139 140 #define CONFIG_SYS_HZ 1000 141 142 #define CONFIG_CMDLINE_EDITING 1 143 144 /*----------------------------------------------------------------------- 145 * Stack sizes 146 * 147 * The stack sizes are set up in start.S using the settings below 148 */ 149 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ 150 151 /*----------------------------------------------------------------------- 152 * Physical Memory Map 153 */ 154 #define CONFIG_NR_DRAM_BANKS 1 155 #define PHYS_SDRAM_1 CSD0_BASE 156 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 157 #define CONFIG_BOARD_EARLY_INIT_F 1 158 159 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 160 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 161 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 162 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 163 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) 164 165 /*----------------------------------------------------------------------- 166 * FLASH and environment organization 167 */ 168 /* No NOR flash present */ 169 #define CONFIG_SYS_NO_FLASH 1 170 171 #define CONFIG_ENV_IS_IN_NAND 1 172 #define CONFIG_ENV_OFFSET 0x40000 173 #define CONFIG_ENV_OFFSET_REDUND 0x60000 174 #define CONFIG_ENV_SIZE (128 * 1024) 175 176 /* 177 * NAND driver 178 */ 179 #define CONFIG_NAND_MXC 180 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 181 #define CONFIG_SYS_MAX_NAND_DEVICE 1 182 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 183 #define CONFIG_MXC_NAND_HWECC 184 #define CONFIG_SYS_NAND_LARGEPAGE 185 186 /* NAND configuration for the NAND_SPL */ 187 188 /* Start copying real U-boot from the second page */ 189 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 190 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 191 /* Load U-Boot to this address */ 192 #define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000 193 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 194 195 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 196 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 197 #define CONFIG_SYS_NAND_PAGE_COUNT 64 198 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 199 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 200 201 202 /* Configuration of lowlevel_init.S (clocks and SDRAM) */ 203 #define CCM_CCMR_SETUP 0x074B0BF5 204 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \ 205 PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \ 206 PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \ 207 PDR0_MCU_PODF(0)) 208 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 209 PLL_MFN(12)) 210 211 #define ESDMISC_MDDR_SETUP 0x00000004 212 #define ESDMISC_MDDR_RESET_DL 0x0000000c 213 #define ESDCFG0_MDDR_SETUP 0x006ac73a 214 215 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 216 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 217 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 218 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 219 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 220 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 221 #define ESDCTL_RW ESDCTL_SETTINGS 222 223 #endif /* __CONFIG_H */ 224