1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 4 * 5 * (C) Copyright 2004 6 * Texas Instruments. 7 * Richard Woodruff <r-woodruff2@ti.com> 8 * Kshitij Gupta <kshitij@ti.com> 9 * 10 * Configuration settings for the Freescale i.MX31 PDK board. 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #include <asm/arch/imx-regs.h> 17 18 /* High Level Configuration Options */ 19 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 20 #define CONFIG_SETUP_MEMORY_TAGS 21 #define CONFIG_INITRD_TAG 22 23 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS 24 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SPL_MAX_SIZE 2048 27 28 #define CONFIG_SPL_TEXT_BASE 0x87dc0000 29 30 #ifndef CONFIG_SPL_BUILD 31 #define CONFIG_SKIP_LOWLEVEL_INIT 32 #endif 33 34 /* 35 * Size of malloc() pool 36 */ 37 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 38 39 /* 40 * Hardware drivers 41 */ 42 43 #define CONFIG_MXC_UART 44 #define CONFIG_MXC_UART_BASE UART1_BASE 45 46 #define CONFIG_DEFAULT_SPI_BUS 1 47 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 48 49 /* PMIC Controller */ 50 #define CONFIG_POWER 51 #define CONFIG_POWER_SPI 52 #define CONFIG_POWER_FSL 53 #define CONFIG_FSL_PMIC_BUS 1 54 #define CONFIG_FSL_PMIC_CS 2 55 #define CONFIG_FSL_PMIC_CLK 1000000 56 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 57 #define CONFIG_FSL_PMIC_BITLEN 32 58 #define CONFIG_RTC_MC13XXX 59 60 /* allow to overwrite serial and ethaddr */ 61 #define CONFIG_ENV_OVERWRITE 62 63 #define CONFIG_EXTRA_ENV_SETTINGS \ 64 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 65 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 66 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 67 "bootcmd=run bootcmd_net\0" \ 68 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 69 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 70 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ 71 "nand erase 0x0 0x40000; " \ 72 "nand write 0x81000000 0x0 0x40000\0" 73 74 /* 75 * Miscellaneous configurable options 76 */ 77 78 /* memtest works on */ 79 #define CONFIG_SYS_MEMTEST_START 0x80000000 80 #define CONFIG_SYS_MEMTEST_END 0x80010000 81 82 /* default load address */ 83 #define CONFIG_SYS_LOAD_ADDR 0x81000000 84 85 /*----------------------------------------------------------------------- 86 * Physical Memory Map 87 */ 88 #define PHYS_SDRAM_1 CSD0_BASE 89 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 90 91 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 92 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 93 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 94 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 95 GENERATED_GBL_DATA_SIZE) 96 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 97 CONFIG_SYS_INIT_RAM_SIZE) 98 99 /* 100 * environment organization 101 */ 102 #define CONFIG_ENV_OFFSET 0x40000 103 #define CONFIG_ENV_OFFSET_REDUND 0x60000 104 #define CONFIG_ENV_SIZE (128 * 1024) 105 106 /* 107 * NAND driver 108 */ 109 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 110 #define CONFIG_SYS_MAX_NAND_DEVICE 1 111 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 112 #define CONFIG_MXC_NAND_HWECC 113 #define CONFIG_SYS_NAND_LARGEPAGE 114 115 /* NAND configuration for the NAND_SPL */ 116 117 /* Start copying real U-Boot from the second page */ 118 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 119 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 120 /* Load U-Boot to this address */ 121 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 122 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 123 124 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 125 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 126 #define CONFIG_SYS_NAND_PAGE_COUNT 64 127 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 128 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 129 130 /* Configuration of lowlevel_init.S (clocks and SDRAM) */ 131 #define CCM_CCMR_SETUP 0x074B0BF5 132 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ 133 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ 134 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ 135 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) 136 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 137 PLL_MFN(12)) 138 139 #define ESDMISC_MDDR_SETUP 0x00000004 140 #define ESDMISC_MDDR_RESET_DL 0x0000000c 141 #define ESDCFG0_MDDR_SETUP 0x006ac73a 142 143 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 144 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 145 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 146 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 147 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 148 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 149 #define ESDCTL_RW ESDCTL_SETTINGS 150 151 #endif /* __CONFIG_H */ 152