1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 4 * 5 * (C) Copyright 2004 6 * Texas Instruments. 7 * Richard Woodruff <r-woodruff2@ti.com> 8 * Kshitij Gupta <kshitij@ti.com> 9 * 10 * Configuration settings for the Freescale i.MX31 PDK board. 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #include <asm/arch/imx-regs.h> 17 18 /* High Level Configuration Options */ 19 #define CONFIG_MX31 /* This is a mx31 */ 20 21 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 22 #define CONFIG_SETUP_MEMORY_TAGS 23 #define CONFIG_INITRD_TAG 24 25 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS 26 27 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 28 #define CONFIG_SPL_MAX_SIZE 2048 29 30 #define CONFIG_SPL_TEXT_BASE 0x87dc0000 31 32 #ifndef CONFIG_SPL_BUILD 33 #define CONFIG_SKIP_LOWLEVEL_INIT 34 #endif 35 36 /* 37 * Size of malloc() pool 38 */ 39 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 40 41 /* 42 * Hardware drivers 43 */ 44 45 #define CONFIG_MXC_UART 46 #define CONFIG_MXC_UART_BASE UART1_BASE 47 48 #define CONFIG_HARD_SPI 49 #define CONFIG_DEFAULT_SPI_BUS 1 50 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 51 52 /* PMIC Controller */ 53 #define CONFIG_POWER 54 #define CONFIG_POWER_SPI 55 #define CONFIG_POWER_FSL 56 #define CONFIG_FSL_PMIC_BUS 1 57 #define CONFIG_FSL_PMIC_CS 2 58 #define CONFIG_FSL_PMIC_CLK 1000000 59 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 60 #define CONFIG_FSL_PMIC_BITLEN 32 61 #define CONFIG_RTC_MC13XXX 62 63 /* allow to overwrite serial and ethaddr */ 64 #define CONFIG_ENV_OVERWRITE 65 66 #define CONFIG_EXTRA_ENV_SETTINGS \ 67 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 68 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 69 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 70 "bootcmd=run bootcmd_net\0" \ 71 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 72 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 73 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ 74 "nand erase 0x0 0x40000; " \ 75 "nand write 0x81000000 0x0 0x40000\0" 76 77 /* 78 * Miscellaneous configurable options 79 */ 80 81 /* memtest works on */ 82 #define CONFIG_SYS_MEMTEST_START 0x80000000 83 #define CONFIG_SYS_MEMTEST_END 0x80010000 84 85 /* default load address */ 86 #define CONFIG_SYS_LOAD_ADDR 0x81000000 87 88 /*----------------------------------------------------------------------- 89 * Physical Memory Map 90 */ 91 #define CONFIG_NR_DRAM_BANKS 1 92 #define PHYS_SDRAM_1 CSD0_BASE 93 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 94 95 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 96 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 97 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 98 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 99 GENERATED_GBL_DATA_SIZE) 100 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 101 CONFIG_SYS_INIT_RAM_SIZE) 102 103 /* 104 * environment organization 105 */ 106 #define CONFIG_ENV_OFFSET 0x40000 107 #define CONFIG_ENV_OFFSET_REDUND 0x60000 108 #define CONFIG_ENV_SIZE (128 * 1024) 109 110 /* 111 * NAND driver 112 */ 113 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 114 #define CONFIG_SYS_MAX_NAND_DEVICE 1 115 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 116 #define CONFIG_MXC_NAND_HWECC 117 #define CONFIG_SYS_NAND_LARGEPAGE 118 119 /* NAND configuration for the NAND_SPL */ 120 121 /* Start copying real U-Boot from the second page */ 122 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 123 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 124 /* Load U-Boot to this address */ 125 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 126 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 127 128 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 129 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 130 #define CONFIG_SYS_NAND_PAGE_COUNT 64 131 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 132 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 133 134 /* Configuration of lowlevel_init.S (clocks and SDRAM) */ 135 #define CCM_CCMR_SETUP 0x074B0BF5 136 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ 137 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ 138 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ 139 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) 140 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 141 PLL_MFN(12)) 142 143 #define ESDMISC_MDDR_SETUP 0x00000004 144 #define ESDMISC_MDDR_RESET_DL 0x0000000c 145 #define ESDCFG0_MDDR_SETUP 0x006ac73a 146 147 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 148 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 149 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 150 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 151 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 152 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 153 #define ESDCTL_RW ESDCTL_SETTINGS 154 155 #endif /* __CONFIG_H */ 156