1 /* 2 * Configuation settings for the Hitachi Solution Engine 7720 3 * 4 * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __MS7720SE_H 10 #define __MS7720SE_H 11 12 #define CONFIG_CPU_SH7720 1 13 #define CONFIG_MS7720SE 1 14 15 #define CONFIG_CMD_FLASH 16 #define CONFIG_CMD_SAVEENV 17 #define CONFIG_CMD_SDRAM 18 #define CONFIG_CMD_MEMORY 19 #define CONFIG_CMD_CACHE 20 #define CONFIG_CMD_PCMCIA 21 #define CONFIG_CMD_IDE 22 #define CONFIG_CMD_EXT2 23 24 #define CONFIG_BAUDRATE 115200 25 #define CONFIG_BOOTARGS "console=ttySC0,115200" 26 #define CONFIG_BOOTFILE "/boot/zImage" 27 #define CONFIG_LOADADDR 0x8E000000 28 29 #define CONFIG_VERSION_VARIABLE 30 #undef CONFIG_SHOW_BOOT_PROGRESS 31 32 /* MEMORY */ 33 #define MS7720SE_SDRAM_BASE 0x8C000000 34 #define MS7720SE_FLASH_BASE_1 0xA0000000 35 #define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024) 36 37 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 38 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 39 #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 40 #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 41 #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 42 /* Buffer size for Boot Arguments passed to kernel */ 43 #define CONFIG_SYS_BARGSIZE 512 44 /* List of legal baudrate settings for this board */ 45 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 46 47 /* SCIF */ 48 #define CONFIG_SCIF_CONSOLE 1 49 #define CONFIG_CONS_SCIF0 1 50 51 #define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE 52 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 53 54 #define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE 55 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 56 57 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 58 #define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1 59 #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 60 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 61 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 62 63 64 /* FLASH */ 65 #define CONFIG_SYS_FLASH_CFI 66 #define CONFIG_FLASH_CFI_DRIVER 67 #undef CONFIG_SYS_FLASH_QUIET_TEST 68 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 69 70 #define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1 71 72 #define CONFIG_SYS_MAX_FLASH_SECT 150 73 #define CONFIG_SYS_MAX_FLASH_BANKS 1 74 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 75 76 #define CONFIG_ENV_IS_IN_FLASH 77 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 78 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 79 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 80 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 81 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 82 83 /* Board Clock */ 84 #define CONFIG_SYS_CLK_FREQ 33333333 85 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 86 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 87 #define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */ 88 89 /* PCMCIA */ 90 #define CONFIG_IDE_PCMCIA 1 91 #define CONFIG_MARUBUN_PCCARD 1 92 #define CONFIG_PCMCIA_SLOT_A 1 93 #define CONFIG_SYS_IDE_MAXDEVICE 1 94 #define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0 95 #define CONFIG_SYS_MARUBUN_MW1 0xb8400000 96 #define CONFIG_SYS_MARUBUN_MW2 0xb8500000 97 #define CONFIG_SYS_MARUBUN_IO 0xb8600000 98 99 #define CONFIG_SYS_PIO_MODE 1 100 #define CONFIG_SYS_IDE_MAXBUS 1 101 #define CONFIG_DOS_PARTITION 1 102 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */ 103 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ 104 #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ 105 #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ 106 #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ 107 #define CONFIG_IDE_SWAP_IO 108 109 #endif /* __MS7720SE_H */ 110