1 /* 2 * Configuation settings for the Hitachi Solution Engine 7720 3 * 4 * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __MS7720SE_H 10 #define __MS7720SE_H 11 12 #define CONFIG_CPU_SH7720 1 13 #define CONFIG_MS7720SE 1 14 15 #define CONFIG_BOOTARGS "console=ttySC0,115200" 16 #define CONFIG_BOOTFILE "/boot/zImage" 17 #define CONFIG_LOADADDR 0x8E000000 18 19 #define CONFIG_DISPLAY_BOARDINFO 20 #undef CONFIG_SHOW_BOOT_PROGRESS 21 22 /* MEMORY */ 23 #define MS7720SE_SDRAM_BASE 0x8C000000 24 #define MS7720SE_FLASH_BASE_1 0xA0000000 25 #define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024) 26 27 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 28 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 29 #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 30 #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 31 #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 32 /* Buffer size for Boot Arguments passed to kernel */ 33 #define CONFIG_SYS_BARGSIZE 512 34 /* List of legal baudrate settings for this board */ 35 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 36 37 /* SCIF */ 38 #define CONFIG_CONS_SCIF0 1 39 40 #define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE 41 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 42 43 #define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE 44 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 45 46 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 47 #define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1 48 #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 49 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 50 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 51 52 /* FLASH */ 53 #define CONFIG_SYS_FLASH_CFI 54 #define CONFIG_FLASH_CFI_DRIVER 55 #undef CONFIG_SYS_FLASH_QUIET_TEST 56 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 57 58 #define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1 59 60 #define CONFIG_SYS_MAX_FLASH_SECT 150 61 #define CONFIG_SYS_MAX_FLASH_BANKS 1 62 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 63 64 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 65 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 66 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 67 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 68 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 69 70 /* Board Clock */ 71 #define CONFIG_SYS_CLK_FREQ 33333333 72 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 73 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 74 #define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */ 75 76 /* PCMCIA */ 77 #define CONFIG_IDE_PCMCIA 1 78 #define CONFIG_MARUBUN_PCCARD 1 79 #define CONFIG_PCMCIA_SLOT_A 1 80 #define CONFIG_SYS_IDE_MAXDEVICE 1 81 #define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0 82 #define CONFIG_SYS_MARUBUN_MW1 0xb8400000 83 #define CONFIG_SYS_MARUBUN_MW2 0xb8500000 84 #define CONFIG_SYS_MARUBUN_IO 0xb8600000 85 86 #define CONFIG_SYS_PIO_MODE 1 87 #define CONFIG_SYS_IDE_MAXBUS 1 88 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */ 89 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ 90 #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ 91 #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ 92 #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ 93 #define CONFIG_IDE_SWAP_IO 94 95 #endif /* __MS7720SE_H */ 96