xref: /openbmc/u-boot/include/configs/mpr2.h (revision 44262327)
1 /*
2  * Configuation settings for MPR2
3  *
4  * Copyright (C) 2008
5  * Mark Jonas <mark.jonas@de.bosch.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __MPR2_H
11 #define __MPR2_H
12 
13 /* Supported commands */
14 
15 /* Default environment variables */
16 #define CONFIG_BOOTFILE		"/boot/zImage"
17 #define CONFIG_LOADADDR		0x8E000000
18 
19 /* CPU and platform */
20 #define CONFIG_CPU_SH7720	1
21 #define CONFIG_MPR2		1
22 
23 #define CONFIG_DISPLAY_BOARDINFO
24 
25 /* U-Boot internals */
26 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
27 #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
28 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
29 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
30 #define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
31 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
32 
33 #define CONFIG_SYS_TEXT_BASE	0x8FFC0000
34 
35 /* Memory */
36 #define CONFIG_SYS_SDRAM_BASE		0x8C000000
37 #define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
38 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
39 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
40 
41 /* Flash */
42 #define CONFIG_SYS_FLASH_CFI
43 #define CONFIG_FLASH_CFI_DRIVER
44 #define CONFIG_SYS_FLASH_EMPTY_INFO
45 #define CONFIG_SYS_FLASH_BASE		0xA0000000
46 #define CONFIG_SYS_MAX_FLASH_SECT	256
47 #define CONFIG_SYS_MAX_FLASH_BANKS	1
48 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
49 #define CONFIG_ENV_SECT_SIZE	(128 * 1024)
50 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
51 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
52 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000
53 #define CONFIG_SYS_FLASH_WRITE_TOUT	500
54 
55 /* Clocks */
56 #define CONFIG_SYS_CLK_FREQ	24000000
57 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
58 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
59 #define CONFIG_SYS_TMU_CLK_DIV		4	/* 4 (default), 16, 64, 256 or 1024 */
60 
61 /* UART */
62 #define CONFIG_CONS_SCIF0	1
63 
64 #endif	/* __MPR2_H */
65