1 /* 2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4 * 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef __CONFIG_H 26 #define __CONFIG_H 27 28 /* 29 * High Level Configuration Options 30 */ 31 #define CONFIG_E300 1 /* E300 family */ 32 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 33 #define CONFIG_MPC830x 1 /* MPC830x family */ 34 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 35 #define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */ 36 37 #ifndef CONFIG_SYS_TEXT_BASE 38 #define CONFIG_SYS_TEXT_BASE 0xFC000000 39 #endif 40 41 /* 42 * On-board devices 43 * 44 * TSECs 45 */ 46 #define CONFIG_TSEC1 47 #define CONFIG_TSEC2 48 49 /* 50 * System Clock Setup 51 */ 52 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 53 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 54 55 /* 56 * Hardware Reset Configuration Word 57 * if CLKIN is 66.66MHz, then 58 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 59 * We choose the A type silicon as default, so the core is 400Mhz. 60 */ 61 #define CONFIG_SYS_HRCW_LOW (\ 62 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 63 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 64 HRCWL_SVCOD_DIV_2 |\ 65 HRCWL_CSB_TO_CLKIN_4X1 |\ 66 HRCWL_CORE_TO_CSB_3X1) 67 /* 68 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 69 * in 8308's HRCWH according to the manual, but original Freescale's 70 * code has them and I've expirienced some problems using the board 71 * with BDI3000 attached when I've tried to set these bits to zero 72 * (UART doesn't work after the 'reset run' command). 73 */ 74 #define CONFIG_SYS_HRCW_HIGH (\ 75 HRCWH_PCI_HOST |\ 76 HRCWH_PCI1_ARBITER_ENABLE |\ 77 HRCWH_CORE_ENABLE |\ 78 HRCWH_FROM_0X00000100 |\ 79 HRCWH_BOOTSEQ_DISABLE |\ 80 HRCWH_SW_WATCHDOG_DISABLE |\ 81 HRCWH_ROM_LOC_LOCAL_16BIT |\ 82 HRCWH_RL_EXT_LEGACY |\ 83 HRCWH_TSEC1M_IN_MII |\ 84 HRCWH_TSEC2M_IN_MII |\ 85 HRCWH_BIG_ENDIAN) 86 87 /* 88 * System IO Config 89 */ 90 #define CONFIG_SYS_SICRH (\ 91 SICRH_ESDHC_A_GPIO |\ 92 SICRH_ESDHC_B_GPIO |\ 93 SICRH_ESDHC_C_GTM |\ 94 SICRH_GPIO_A_TSEC2 |\ 95 SICRH_GPIO_B_TSEC2_TX_CLK |\ 96 SICRH_IEEE1588_A_GPIO |\ 97 SICRH_USB |\ 98 SICRH_GTM_GPIO |\ 99 SICRH_IEEE1588_B_GPIO |\ 100 SICRH_ETSEC2_CRS |\ 101 SICRH_GPIOSEL_1 |\ 102 SICRH_TMROBI_V3P3 |\ 103 SICRH_TSOBI1_V3P3 |\ 104 SICRH_TSOBI2_V3P3) /* 0xf577d100 */ 105 #define CONFIG_SYS_SICRL (\ 106 SICRL_SPI_PF0 |\ 107 SICRL_UART_PF0 |\ 108 SICRL_IRQ_PF0 |\ 109 SICRL_I2C2_PF0 |\ 110 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ 111 112 #define CONFIG_SYS_GPIO1_PRELIM 113 /* GPIO Default input/output settings */ 114 #define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00 115 /* 116 * Default GPIO values: 117 * LED#1 enabled; WLAN enabled; Both COM LED on (orange) 118 */ 119 #define CONFIG_SYS_GPIO1_DAT 0x08008C00 120 121 /* 122 * IMMR new address 123 */ 124 #define CONFIG_SYS_IMMR 0xE0000000 125 126 /* 127 * SERDES 128 */ 129 #define CONFIG_FSL_SERDES 130 #define CONFIG_FSL_SERDES1 0xe3000 131 132 /* 133 * Arbiter Setup 134 */ 135 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 136 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 137 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 138 139 /* 140 * DDR Setup 141 */ 142 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 143 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 144 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 145 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 146 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 147 | DDRCDR_PZ_LOZ \ 148 | DDRCDR_NZ_LOZ \ 149 | DDRCDR_ODT \ 150 | DDRCDR_Q_DRN) 151 /* 0x7b880001 */ 152 /* 153 * Manually set up DDR parameters 154 * consist of two chips HY5PS12621BFP-C4 from HYNIX 155 */ 156 157 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 158 159 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 160 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 161 | CSCONFIG_ODT_RD_NEVER \ 162 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 163 | CSCONFIG_ROW_BIT_13 \ 164 | CSCONFIG_COL_BIT_10) 165 /* 0x80010102 */ 166 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 167 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 168 | (0 << TIMING_CFG0_WRT_SHIFT) \ 169 | (0 << TIMING_CFG0_RRT_SHIFT) \ 170 | (0 << TIMING_CFG0_WWT_SHIFT) \ 171 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 172 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 173 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 174 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 175 /* 0x00220802 */ 176 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 177 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 178 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 179 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 180 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 181 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 182 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 183 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 184 /* 0x27256222 */ 185 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 186 | (4 << TIMING_CFG2_CPO_SHIFT) \ 187 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 188 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 189 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 190 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 191 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 192 /* 0x121048c5 */ 193 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 194 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 195 /* 0x03600100 */ 196 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 197 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 198 | SDRAM_CFG_DBW_32) 199 /* 0x43080000 */ 200 201 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 202 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 203 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 204 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 205 #define CONFIG_SYS_DDR_MODE2 0x00000000 206 207 /* 208 * Memory test 209 */ 210 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 211 #define CONFIG_SYS_MEMTEST_END 0x07f00000 212 213 /* 214 * The reserved memory 215 */ 216 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 217 218 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 219 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 220 221 /* 222 * Initial RAM Base Address Setup 223 */ 224 #define CONFIG_SYS_INIT_RAM_LOCK 1 225 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 226 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 227 #define CONFIG_SYS_GBL_DATA_OFFSET \ 228 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 229 230 /* 231 * Local Bus Configuration & Clock Setup 232 */ 233 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 234 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 235 #define CONFIG_SYS_LBC_LBCR 0x00040000 236 237 /* 238 * FLASH on the Local Bus 239 */ 240 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 241 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 242 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 243 244 #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ 245 #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ 246 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 247 248 /* Window base at flash base */ 249 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 250 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) 251 252 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 253 | BR_PS_16 /* 16 bit port */ \ 254 | BR_MS_GPCM /* MSEL = GPCM */ \ 255 | BR_V) /* valid */ 256 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 257 | OR_UPM_XAM \ 258 | OR_GPCM_CSNT \ 259 | OR_GPCM_ACS_DIV2 \ 260 | OR_GPCM_XACS \ 261 | OR_GPCM_SCY_4 \ 262 | OR_GPCM_TRLX_SET \ 263 | OR_GPCM_EHTR_SET) 264 265 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 266 #define CONFIG_SYS_MAX_FLASH_SECT 512 267 268 /* Flash Erase Timeout (ms) */ 269 #define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024) 270 /* Flash Write Timeout (ms) */ 271 #define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024) 272 273 /* 274 * SJA1000 CAN controller on Local Bus 275 */ 276 #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 277 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SJA1000_BASE \ 278 | BR_PS_8 /* 8 bit port size */ \ 279 | BR_MS_GPCM /* MSEL = GPCM */ \ 280 | BR_V) /* valid */ 281 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 282 | OR_GPCM_SCY_5 \ 283 | OR_GPCM_EHTR_SET) 284 /* 0xFFFF8052 */ 285 286 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE 287 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 288 289 /* 290 * CPLD on Local Bus 291 */ 292 #define CONFIG_SYS_CPLD_BASE 0xFBFF8000 293 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_CPLD_BASE \ 294 | BR_PS_8 /* 8 bit port */ \ 295 | BR_MS_GPCM /* MSEL = GPCM */ \ 296 | BR_V) /* valid */ 297 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \ 298 | OR_GPCM_SCY_4 \ 299 | OR_GPCM_EHTR_SET) 300 /* 0xFFFF8042 */ 301 302 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE 303 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 304 305 /* 306 * Serial Port 307 */ 308 #define CONFIG_CONS_INDEX 1 309 #undef CONFIG_SERIAL_SOFTWARE_FIFO 310 #define CONFIG_SYS_NS16550 311 #define CONFIG_SYS_NS16550_SERIAL 312 #define CONFIG_SYS_NS16550_REG_SIZE 1 313 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 314 315 #define CONFIG_SYS_BAUDRATE_TABLE \ 316 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 317 318 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 319 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 320 321 /* Use the HUSH parser */ 322 #define CONFIG_SYS_HUSH_PARSER 323 324 /* Pass open firmware flat tree */ 325 #define CONFIG_OF_LIBFDT 1 326 #define CONFIG_OF_BOARD_SETUP 1 327 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 328 329 /* I2C */ 330 #define CONFIG_HARD_I2C /* I2C with hardware support */ 331 #define CONFIG_FSL_I2C 332 #define CONFIG_I2C_MULTI_BUS 333 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 334 #define CONFIG_SYS_I2C_SLAVE 0x7F 335 #define CONFIG_SYS_I2C_OFFSET 0x3000 336 #define CONFIG_SYS_I2C2_OFFSET 0x3100 337 338 /* 339 * General PCI 340 * Addresses are mapped 1-1. 341 */ 342 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 343 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 344 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 345 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 346 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 347 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 348 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 349 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 350 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 351 352 /* enable PCIE clock */ 353 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 354 355 #define CONFIG_PCI 356 #define CONFIG_PCI_INDIRECT_BRIDGE 357 #define CONFIG_PCIE 358 359 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 360 361 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 362 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 363 364 /* 365 * TSEC 366 */ 367 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 368 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 369 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 370 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 371 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 372 373 /* 374 * TSEC ethernet configuration 375 */ 376 #define CONFIG_MII 1 /* MII PHY management */ 377 #define CONFIG_TSEC1_NAME "eTSEC0" 378 #define CONFIG_TSEC2_NAME "eTSEC1" 379 #define TSEC1_PHY_ADDR 1 380 #define TSEC2_PHY_ADDR 2 381 #define TSEC1_PHYIDX 0 382 #define TSEC2_PHYIDX 0 383 #define TSEC1_FLAGS 0 384 #define TSEC2_FLAGS 0 385 386 /* Options are: eTSEC[0-1] */ 387 #define CONFIG_ETHPRIME "eTSEC0" 388 389 /* 390 * Environment 391 */ 392 #define CONFIG_ENV_IS_IN_FLASH 1 393 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 394 CONFIG_SYS_MONITOR_LEN) 395 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 396 #define CONFIG_ENV_SIZE 0x2000 397 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 398 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 399 400 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 401 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 402 403 /* 404 * BOOTP options 405 */ 406 #define CONFIG_BOOTP_BOOTFILESIZE 407 #define CONFIG_BOOTP_BOOTPATH 408 #define CONFIG_BOOTP_GATEWAY 409 #define CONFIG_BOOTP_HOSTNAME 410 411 /* 412 * Command line configuration. 413 */ 414 #include <config_cmd_default.h> 415 416 #define CONFIG_CMD_DHCP 417 #define CONFIG_CMD_I2C 418 #define CONFIG_CMD_MII 419 #define CONFIG_CMD_NET 420 #define CONFIG_CMD_PCI 421 #define CONFIG_CMD_PING 422 423 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 424 425 /* 426 * Miscellaneous configurable options 427 */ 428 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 429 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 430 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 431 432 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 433 434 /* Print Buffer Size */ 435 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 436 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 437 /* Boot Argument Buffer Size */ 438 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 439 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 440 441 /* 442 * For booting Linux, the board info and command line data 443 * have to be in the first 8 MB of memory, since this is 444 * the maximum mapped by the Linux kernel during initialization. 445 */ 446 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 447 448 /* 449 * Core HID Setup 450 */ 451 #define CONFIG_SYS_HID0_INIT 0x000000000 452 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 453 HID0_ENABLE_INSTRUCTION_CACHE | \ 454 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 455 #define CONFIG_SYS_HID2 HID2_HBE 456 457 /* 458 * MMU Setup 459 */ 460 461 /* DDR: cache cacheable */ 462 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 463 BATL_MEMCOHERENCE) 464 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 465 BATU_VS | BATU_VP) 466 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 467 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 468 469 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 470 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 471 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 472 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 473 BATU_VP) 474 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 475 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 476 477 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 478 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 479 BATL_MEMCOHERENCE) 480 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 481 BATU_VS | BATU_VP) 482 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 483 BATL_CACHEINHIBIT | \ 484 BATL_GUARDEDSTORAGE) 485 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 486 487 /* Stack in dcache: cacheable, no memory coherence */ 488 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 489 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 490 BATU_VS | BATU_VP) 491 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 492 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 493 494 /* 495 * Environment Configuration 496 */ 497 498 #define CONFIG_ENV_OVERWRITE 499 500 #if defined(CONFIG_TSEC_ENET) 501 #define CONFIG_HAS_ETH0 502 #define CONFIG_HAS_ETH1 503 #endif 504 505 #define CONFIG_BAUDRATE 115200 506 507 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 508 509 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 510 511 #define CONFIG_EXTRA_ENV_SETTINGS \ 512 "netdev=eth0\0" \ 513 "consoledev=ttyS0\0" \ 514 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 515 "nfsroot=${serverip}:${rootpath}\0" \ 516 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 517 "addip=setenv bootargs ${bootargs} " \ 518 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 519 ":${hostname}:${netdev}:off panic=1\0" \ 520 "addtty=setenv bootargs ${bootargs}" \ 521 " console=${consoledev},${baudrate}\0" \ 522 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 523 "addmisc=setenv bootargs ${bootargs}\0" \ 524 "kernel_addr=FC0A0000\0" \ 525 "fdt_addr=FC2A0000\0" \ 526 "ramdisk_addr=FC2C0000\0" \ 527 "u-boot=mpc8308_p1m/u-boot.bin\0" \ 528 "kernel_addr_r=1000000\0" \ 529 "fdt_addr_r=C00000\0" \ 530 "hostname=mpc8308_p1m\0" \ 531 "bootfile=mpc8308_p1m/uImage\0" \ 532 "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \ 533 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 534 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 535 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 536 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 537 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 538 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 539 "tftp ${fdt_addr_r} ${fdtfile};" \ 540 "run nfsargs addip addtty addmtd addmisc;" \ 541 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 542 "bootcmd=run flash_self\0" \ 543 "load=tftp ${loadaddr} ${u-boot}\0" \ 544 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 545 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 546 " +${filesize};cp.b ${fileaddr} " \ 547 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 548 "upd=run load update\0" \ 549 550 #endif /* __CONFIG_H */ 551