1 /*
2  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
3  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
4  *
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 #define CONFIG_SYS_GENERIC_BOARD
13 #define CONFIG_DISPLAY_BOARDINFO
14 
15 /*
16  * High Level Configuration Options
17  */
18 #define CONFIG_E300		1 /* E300 family */
19 #define CONFIG_MPC830x		1 /* MPC830x family */
20 #define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
21 #define CONFIG_MPC8308_P1M	1 /* mpc8308_p1m board specific */
22 
23 #ifndef CONFIG_SYS_TEXT_BASE
24 #define CONFIG_SYS_TEXT_BASE	0xFC000000
25 #endif
26 
27 /*
28  * On-board devices
29  *
30  * TSECs
31  */
32 #define CONFIG_TSEC1
33 #define CONFIG_TSEC2
34 
35 /*
36  * System Clock Setup
37  */
38 #define CONFIG_83XX_CLKIN	33333333 /* in Hz */
39 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
40 
41 /*
42  * Hardware Reset Configuration Word
43  * if CLKIN is 66.66MHz, then
44  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
45  * We choose the A type silicon as default, so the core is 400Mhz.
46  */
47 #define CONFIG_SYS_HRCW_LOW (\
48 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
49 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
50 	HRCWL_SVCOD_DIV_2 |\
51 	HRCWL_CSB_TO_CLKIN_4X1 |\
52 	HRCWL_CORE_TO_CSB_3X1)
53 /*
54  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
55  * in 8308's HRCWH according to the manual, but original Freescale's
56  * code has them and I've expirienced some problems using the board
57  * with BDI3000 attached when I've tried to set these bits to zero
58  * (UART doesn't work after the 'reset run' command).
59  */
60 #define CONFIG_SYS_HRCW_HIGH (\
61 	HRCWH_PCI_HOST |\
62 	HRCWH_PCI1_ARBITER_ENABLE |\
63 	HRCWH_CORE_ENABLE |\
64 	HRCWH_FROM_0X00000100 |\
65 	HRCWH_BOOTSEQ_DISABLE |\
66 	HRCWH_SW_WATCHDOG_DISABLE |\
67 	HRCWH_ROM_LOC_LOCAL_16BIT |\
68 	HRCWH_RL_EXT_LEGACY |\
69 	HRCWH_TSEC1M_IN_MII |\
70 	HRCWH_TSEC2M_IN_MII |\
71 	HRCWH_BIG_ENDIAN)
72 
73 /*
74  * System IO Config
75  */
76 #define CONFIG_SYS_SICRH (\
77 	SICRH_ESDHC_A_GPIO |\
78 	SICRH_ESDHC_B_GPIO |\
79 	SICRH_ESDHC_C_GTM |\
80 	SICRH_GPIO_A_TSEC2 |\
81 	SICRH_GPIO_B_TSEC2_TX_CLK |\
82 	SICRH_IEEE1588_A_GPIO |\
83 	SICRH_USB |\
84 	SICRH_GTM_GPIO |\
85 	SICRH_IEEE1588_B_GPIO |\
86 	SICRH_ETSEC2_CRS |\
87 	SICRH_GPIOSEL_1 |\
88 	SICRH_TMROBI_V3P3 |\
89 	SICRH_TSOBI1_V3P3 |\
90 	SICRH_TSOBI2_V3P3)	/* 0xf577d100 */
91 #define CONFIG_SYS_SICRL (\
92 	SICRL_SPI_PF0 |\
93 	SICRL_UART_PF0 |\
94 	SICRL_IRQ_PF0 |\
95 	SICRL_I2C2_PF0 |\
96 	SICRL_ETSEC1_TX_CLK)	/* 0x00000000 */
97 
98 #define CONFIG_SYS_GPIO1_PRELIM
99 /* GPIO Default input/output settings */
100 #define CONFIG_SYS_GPIO1_DIR        0x7AAF8C00
101 /*
102  * Default GPIO values:
103  * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
104  */
105 #define CONFIG_SYS_GPIO1_DAT        0x08008C00
106 
107 /*
108  * IMMR new address
109  */
110 #define CONFIG_SYS_IMMR		0xE0000000
111 
112 /*
113  * SERDES
114  */
115 #define CONFIG_FSL_SERDES
116 #define CONFIG_FSL_SERDES1	0xe3000
117 
118 /*
119  * Arbiter Setup
120  */
121 #define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
122 #define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
123 #define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
124 
125 /*
126  * DDR Setup
127  */
128 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
129 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
130 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
131 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
132 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
133 				| DDRCDR_PZ_LOZ \
134 				| DDRCDR_NZ_LOZ \
135 				| DDRCDR_ODT \
136 				| DDRCDR_Q_DRN)
137 				/* 0x7b880001 */
138 /*
139  * Manually set up DDR parameters
140  * consist of two chips HY5PS12621BFP-C4 from HYNIX
141  */
142 
143 #define CONFIG_SYS_DDR_SIZE		128 /* MB */
144 
145 #define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
146 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
147 					| CSCONFIG_ODT_RD_NEVER \
148 					| CSCONFIG_ODT_WR_ONLY_CURRENT \
149 					| CSCONFIG_ROW_BIT_13 \
150 					| CSCONFIG_COL_BIT_10)
151 					/* 0x80010102 */
152 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
153 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
154 				| (0 << TIMING_CFG0_WRT_SHIFT) \
155 				| (0 << TIMING_CFG0_RRT_SHIFT) \
156 				| (0 << TIMING_CFG0_WWT_SHIFT) \
157 				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
158 				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
159 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
160 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
161 				/* 0x00220802 */
162 #define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
163 				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
164 				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
165 				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
166 				| (6 << TIMING_CFG1_REFREC_SHIFT) \
167 				| (2 << TIMING_CFG1_WRREC_SHIFT) \
168 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
169 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
170 				/* 0x27256222 */
171 #define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
172 				| (4 << TIMING_CFG2_CPO_SHIFT) \
173 				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
174 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
175 				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
176 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
177 				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
178 				/* 0x121048c5 */
179 #define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
180 				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
181 				/* 0x03600100 */
182 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
183 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
184 				| SDRAM_CFG_DBW_32)
185 				/* 0x43080000 */
186 
187 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
188 #define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
189 				| (0x0232 << SDRAM_MODE_SD_SHIFT))
190 				/* ODT 150ohm CL=3, AL=1 on SDRAM */
191 #define CONFIG_SYS_DDR_MODE2		0x00000000
192 
193 /*
194  * Memory test
195  */
196 #define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
197 #define CONFIG_SYS_MEMTEST_END		0x07f00000
198 
199 /*
200  * The reserved memory
201  */
202 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
203 
204 #define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
205 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
206 
207 /*
208  * Initial RAM Base Address Setup
209  */
210 #define CONFIG_SYS_INIT_RAM_LOCK	1
211 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
212 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
213 #define CONFIG_SYS_GBL_DATA_OFFSET	\
214 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
215 
216 /*
217  * Local Bus Configuration & Clock Setup
218  */
219 #define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
220 #define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
221 #define CONFIG_SYS_LBC_LBCR		0x00040000
222 
223 /*
224  * FLASH on the Local Bus
225  */
226 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
227 #define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
228 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
229 
230 #define CONFIG_SYS_FLASH_BASE		0xFC000000 /* FLASH base address */
231 #define CONFIG_SYS_FLASH_SIZE		64 /* FLASH size is 64M */
232 #define CONFIG_SYS_FLASH_PROTECTION	1 /* Use h/w Flash protection. */
233 
234 /* Window base at flash base */
235 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
236 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_64MB)
237 
238 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
239 				| BR_PS_16	/* 16 bit port */ \
240 				| BR_MS_GPCM	/* MSEL = GPCM */ \
241 				| BR_V)		/* valid */
242 #define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
243 				| OR_UPM_XAM \
244 				| OR_GPCM_CSNT \
245 				| OR_GPCM_ACS_DIV2 \
246 				| OR_GPCM_XACS \
247 				| OR_GPCM_SCY_4 \
248 				| OR_GPCM_TRLX_SET \
249 				| OR_GPCM_EHTR_SET)
250 
251 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
252 #define CONFIG_SYS_MAX_FLASH_SECT	512
253 
254 /* Flash Erase Timeout (ms) */
255 #define CONFIG_SYS_FLASH_ERASE_TOUT	(1000 * 1024)
256 /* Flash Write Timeout (ms) */
257 #define CONFIG_SYS_FLASH_WRITE_TOUT	(500 * 1024)
258 
259 /*
260  * SJA1000 CAN controller on Local Bus
261  */
262 #define CONFIG_SYS_SJA1000_BASE	0xFBFF0000
263 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_SJA1000_BASE \
264 				| BR_PS_8	/* 8 bit port size */ \
265 				| BR_MS_GPCM	/* MSEL = GPCM */ \
266 				| BR_V)		/* valid */
267 #define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB \
268 				| OR_GPCM_SCY_5 \
269 				| OR_GPCM_EHTR_SET)
270 				/* 0xFFFF8052 */
271 
272 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_SJA1000_BASE
273 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
274 
275 /*
276  * CPLD on Local Bus
277  */
278 #define CONFIG_SYS_CPLD_BASE	0xFBFF8000
279 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_CPLD_BASE \
280 				| BR_PS_8	/* 8 bit port */ \
281 				| BR_MS_GPCM	/* MSEL = GPCM */ \
282 				| BR_V)		/* valid */
283 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_32KB \
284 				| OR_GPCM_SCY_4 \
285 				| OR_GPCM_EHTR_SET)
286 				/* 0xFFFF8042 */
287 
288 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_CPLD_BASE
289 #define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
290 
291 /*
292  * Serial Port
293  */
294 #define CONFIG_CONS_INDEX	1
295 #undef CONFIG_SERIAL_SOFTWARE_FIFO
296 #define CONFIG_SYS_NS16550
297 #define CONFIG_SYS_NS16550_SERIAL
298 #define CONFIG_SYS_NS16550_REG_SIZE	1
299 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
300 
301 #define CONFIG_SYS_BAUDRATE_TABLE  \
302 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
303 
304 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
305 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
306 
307 /* Use the HUSH parser */
308 #define CONFIG_SYS_HUSH_PARSER
309 
310 /* Pass open firmware flat tree */
311 #define CONFIG_OF_LIBFDT	1
312 #define CONFIG_OF_BOARD_SETUP	1
313 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
314 
315 /* I2C */
316 #define CONFIG_SYS_I2C
317 #define CONFIG_SYS_I2C_FSL
318 #define CONFIG_SYS_FSL_I2C_SPEED	400000
319 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
320 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
321 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
322 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
323 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
324 
325 /*
326  * General PCI
327  * Addresses are mapped 1-1.
328  */
329 #define CONFIG_SYS_PCIE1_BASE		0xA0000000
330 #define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
331 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
332 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
333 #define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
334 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
335 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
336 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
337 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
338 
339 /* enable PCIE clock */
340 #define CONFIG_SYS_SCCR_PCIEXP1CM	1
341 
342 #define CONFIG_PCI
343 #define CONFIG_PCI_INDIRECT_BRIDGE
344 #define CONFIG_PCIE
345 
346 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
347 
348 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
349 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
350 
351 /*
352  * TSEC
353  */
354 #define CONFIG_TSEC_ENET	/* TSEC ethernet support */
355 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
356 #define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
357 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
358 #define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
359 
360 /*
361  * TSEC ethernet configuration
362  */
363 #define CONFIG_MII		1 /* MII PHY management */
364 #define CONFIG_TSEC1_NAME	"eTSEC0"
365 #define CONFIG_TSEC2_NAME	"eTSEC1"
366 #define TSEC1_PHY_ADDR		1
367 #define TSEC2_PHY_ADDR		2
368 #define TSEC1_PHYIDX		0
369 #define TSEC2_PHYIDX		0
370 #define TSEC1_FLAGS		0
371 #define TSEC2_FLAGS		0
372 
373 /* Options are: eTSEC[0-1] */
374 #define CONFIG_ETHPRIME		"eTSEC0"
375 
376 /*
377  * Environment
378  */
379 #define CONFIG_ENV_IS_IN_FLASH	1
380 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
381 				 CONFIG_SYS_MONITOR_LEN)
382 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
383 #define CONFIG_ENV_SIZE		0x2000
384 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
385 #define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
386 
387 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
388 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
389 
390 /*
391  * BOOTP options
392  */
393 #define CONFIG_BOOTP_BOOTFILESIZE
394 #define CONFIG_BOOTP_BOOTPATH
395 #define CONFIG_BOOTP_GATEWAY
396 #define CONFIG_BOOTP_HOSTNAME
397 
398 /*
399  * Command line configuration.
400  */
401 #include <config_cmd_default.h>
402 
403 #define CONFIG_CMD_DHCP
404 #define CONFIG_CMD_I2C
405 #define CONFIG_CMD_MII
406 #define CONFIG_CMD_NET
407 #define CONFIG_CMD_PCI
408 #define CONFIG_CMD_PING
409 
410 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
411 
412 /*
413  * Miscellaneous configurable options
414  */
415 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
416 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
417 
418 #define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
419 
420 /* Print Buffer Size */
421 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
422 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
423 /* Boot Argument Buffer Size */
424 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
425 
426 /*
427  * For booting Linux, the board info and command line data
428  * have to be in the first 8 MB of memory, since this is
429  * the maximum mapped by the Linux kernel during initialization.
430  */
431 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
432 
433 /*
434  * Core HID Setup
435  */
436 #define CONFIG_SYS_HID0_INIT	0x000000000
437 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
438 				 HID0_ENABLE_INSTRUCTION_CACHE | \
439 				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
440 #define CONFIG_SYS_HID2		HID2_HBE
441 
442 /*
443  * MMU Setup
444  */
445 
446 /* DDR: cache cacheable */
447 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
448 					BATL_MEMCOHERENCE)
449 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
450 					BATU_VS | BATU_VP)
451 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
452 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
453 
454 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
455 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_RW | \
456 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
457 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
458 					BATU_VP)
459 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
460 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
461 
462 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
463 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
464 					BATL_MEMCOHERENCE)
465 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
466 					BATU_VS | BATU_VP)
467 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
468 					BATL_CACHEINHIBIT | \
469 					BATL_GUARDEDSTORAGE)
470 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
471 
472 /* Stack in dcache: cacheable, no memory coherence */
473 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
474 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
475 					BATU_VS | BATU_VP)
476 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
477 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
478 
479 /*
480  * Environment Configuration
481  */
482 
483 #define CONFIG_ENV_OVERWRITE
484 
485 #if defined(CONFIG_TSEC_ENET)
486 #define CONFIG_HAS_ETH0
487 #define CONFIG_HAS_ETH1
488 #endif
489 
490 #define CONFIG_BAUDRATE 115200
491 
492 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
493 
494 #define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
495 
496 #define	CONFIG_EXTRA_ENV_SETTINGS					\
497 	"netdev=eth0\0"							\
498 	"consoledev=ttyS0\0"						\
499 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
500 		"nfsroot=${serverip}:${rootpath}\0"			\
501 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
502 	"addip=setenv bootargs ${bootargs} "				\
503 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
504 		":${hostname}:${netdev}:off panic=1\0"			\
505 	"addtty=setenv bootargs ${bootargs}"				\
506 		" console=${consoledev},${baudrate}\0"			\
507 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
508 	"addmisc=setenv bootargs ${bootargs}\0"				\
509 	"kernel_addr=FC0A0000\0"					\
510 	"fdt_addr=FC2A0000\0"						\
511 	"ramdisk_addr=FC2C0000\0"					\
512 	"u-boot=mpc8308_p1m/u-boot.bin\0"				\
513 	"kernel_addr_r=1000000\0"					\
514 	"fdt_addr_r=C00000\0"						\
515 	"hostname=mpc8308_p1m\0"					\
516 	"bootfile=mpc8308_p1m/uImage\0"					\
517 	"fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0"				\
518 	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
519 	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
520 		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
521 	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
522 		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
523 	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
524 		"tftp ${fdt_addr_r} ${fdtfile};"			\
525 		"run nfsargs addip addtty addmtd addmisc;"		\
526 		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
527 	"bootcmd=run flash_self\0"					\
528 	"load=tftp ${loadaddr} ${u-boot}\0"				\
529 	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
530 		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
531 		" +${filesize};cp.b ${fileaddr} "			\
532 		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
533 	"upd=run load update\0"						\
534 
535 #endif	/* __CONFIG_H */
536