1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2bc8f8c26SIlya Yanok /* 3bc8f8c26SIlya Yanok * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 4bc8f8c26SIlya Yanok * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 5bc8f8c26SIlya Yanok * 6bc8f8c26SIlya Yanok */ 7bc8f8c26SIlya Yanok 8bc8f8c26SIlya Yanok #ifndef __CONFIG_H 9bc8f8c26SIlya Yanok #define __CONFIG_H 10bc8f8c26SIlya Yanok 11bc8f8c26SIlya Yanok /* 12bc8f8c26SIlya Yanok * High Level Configuration Options 13bc8f8c26SIlya Yanok */ 14bc8f8c26SIlya Yanok #define CONFIG_E300 1 /* E300 family */ 158afad91fSGerlando Falauto #define CONFIG_MPC830x 1 /* MPC830x family */ 16bc8f8c26SIlya Yanok #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 17bc8f8c26SIlya Yanok 18bc8f8c26SIlya Yanok /* 19bc8f8c26SIlya Yanok * On-board devices 20bc8f8c26SIlya Yanok * 21bc8f8c26SIlya Yanok * TSECs 22bc8f8c26SIlya Yanok */ 23bc8f8c26SIlya Yanok #define CONFIG_TSEC1 24bc8f8c26SIlya Yanok #define CONFIG_TSEC2 25bc8f8c26SIlya Yanok 26bc8f8c26SIlya Yanok /* 27bc8f8c26SIlya Yanok * System Clock Setup 28bc8f8c26SIlya Yanok */ 29bc8f8c26SIlya Yanok #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 30bc8f8c26SIlya Yanok #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 31bc8f8c26SIlya Yanok 32bc8f8c26SIlya Yanok /* 33bc8f8c26SIlya Yanok * Hardware Reset Configuration Word 34bc8f8c26SIlya Yanok * if CLKIN is 66.66MHz, then 35bc8f8c26SIlya Yanok * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 36bc8f8c26SIlya Yanok * We choose the A type silicon as default, so the core is 400Mhz. 37bc8f8c26SIlya Yanok */ 38bc8f8c26SIlya Yanok #define CONFIG_SYS_HRCW_LOW (\ 39bc8f8c26SIlya Yanok HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 40bc8f8c26SIlya Yanok HRCWL_DDR_TO_SCB_CLK_2X1 |\ 41bc8f8c26SIlya Yanok HRCWL_SVCOD_DIV_2 |\ 42bc8f8c26SIlya Yanok HRCWL_CSB_TO_CLKIN_4X1 |\ 43bc8f8c26SIlya Yanok HRCWL_CORE_TO_CSB_3X1) 44bc8f8c26SIlya Yanok /* 45bc8f8c26SIlya Yanok * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 46bc8f8c26SIlya Yanok * in 8308's HRCWH according to the manual, but original Freescale's 47bc8f8c26SIlya Yanok * code has them and I've expirienced some problems using the board 48bc8f8c26SIlya Yanok * with BDI3000 attached when I've tried to set these bits to zero 49bc8f8c26SIlya Yanok * (UART doesn't work after the 'reset run' command). 50bc8f8c26SIlya Yanok */ 51bc8f8c26SIlya Yanok #define CONFIG_SYS_HRCW_HIGH (\ 52bc8f8c26SIlya Yanok HRCWH_PCI_HOST |\ 53bc8f8c26SIlya Yanok HRCWH_PCI1_ARBITER_ENABLE |\ 54bc8f8c26SIlya Yanok HRCWH_CORE_ENABLE |\ 55bc8f8c26SIlya Yanok HRCWH_FROM_0X00000100 |\ 56bc8f8c26SIlya Yanok HRCWH_BOOTSEQ_DISABLE |\ 57bc8f8c26SIlya Yanok HRCWH_SW_WATCHDOG_DISABLE |\ 58bc8f8c26SIlya Yanok HRCWH_ROM_LOC_LOCAL_16BIT |\ 59bc8f8c26SIlya Yanok HRCWH_RL_EXT_LEGACY |\ 60bc8f8c26SIlya Yanok HRCWH_TSEC1M_IN_MII |\ 61bc8f8c26SIlya Yanok HRCWH_TSEC2M_IN_MII |\ 62bc8f8c26SIlya Yanok HRCWH_BIG_ENDIAN) 63bc8f8c26SIlya Yanok 64bc8f8c26SIlya Yanok /* 65bc8f8c26SIlya Yanok * System IO Config 66bc8f8c26SIlya Yanok */ 67bc8f8c26SIlya Yanok #define CONFIG_SYS_SICRH (\ 68bc8f8c26SIlya Yanok SICRH_ESDHC_A_GPIO |\ 69bc8f8c26SIlya Yanok SICRH_ESDHC_B_GPIO |\ 70bc8f8c26SIlya Yanok SICRH_ESDHC_C_GTM |\ 71bc8f8c26SIlya Yanok SICRH_GPIO_A_TSEC2 |\ 72bc8f8c26SIlya Yanok SICRH_GPIO_B_TSEC2_TX_CLK |\ 73bc8f8c26SIlya Yanok SICRH_IEEE1588_A_GPIO |\ 74bc8f8c26SIlya Yanok SICRH_USB |\ 75bc8f8c26SIlya Yanok SICRH_GTM_GPIO |\ 76bc8f8c26SIlya Yanok SICRH_IEEE1588_B_GPIO |\ 77bc8f8c26SIlya Yanok SICRH_ETSEC2_CRS |\ 78bc8f8c26SIlya Yanok SICRH_GPIOSEL_1 |\ 79bc8f8c26SIlya Yanok SICRH_TMROBI_V3P3 |\ 80bc8f8c26SIlya Yanok SICRH_TSOBI1_V3P3 |\ 81bc8f8c26SIlya Yanok SICRH_TSOBI2_V3P3) /* 0xf577d100 */ 82bc8f8c26SIlya Yanok #define CONFIG_SYS_SICRL (\ 83bc8f8c26SIlya Yanok SICRL_SPI_PF0 |\ 84bc8f8c26SIlya Yanok SICRL_UART_PF0 |\ 85bc8f8c26SIlya Yanok SICRL_IRQ_PF0 |\ 86bc8f8c26SIlya Yanok SICRL_I2C2_PF0 |\ 87bc8f8c26SIlya Yanok SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ 88bc8f8c26SIlya Yanok 89bc8f8c26SIlya Yanok #define CONFIG_SYS_GPIO1_PRELIM 90bc8f8c26SIlya Yanok /* GPIO Default input/output settings */ 91bc8f8c26SIlya Yanok #define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00 92bc8f8c26SIlya Yanok /* 93bc8f8c26SIlya Yanok * Default GPIO values: 94bc8f8c26SIlya Yanok * LED#1 enabled; WLAN enabled; Both COM LED on (orange) 95bc8f8c26SIlya Yanok */ 96bc8f8c26SIlya Yanok #define CONFIG_SYS_GPIO1_DAT 0x08008C00 97bc8f8c26SIlya Yanok 98bc8f8c26SIlya Yanok /* 99bc8f8c26SIlya Yanok * IMMR new address 100bc8f8c26SIlya Yanok */ 101bc8f8c26SIlya Yanok #define CONFIG_SYS_IMMR 0xE0000000 102bc8f8c26SIlya Yanok 103bc8f8c26SIlya Yanok /* 104bc8f8c26SIlya Yanok * SERDES 105bc8f8c26SIlya Yanok */ 106bc8f8c26SIlya Yanok #define CONFIG_FSL_SERDES 107bc8f8c26SIlya Yanok #define CONFIG_FSL_SERDES1 0xe3000 108bc8f8c26SIlya Yanok 109bc8f8c26SIlya Yanok /* 110bc8f8c26SIlya Yanok * Arbiter Setup 111bc8f8c26SIlya Yanok */ 112bc8f8c26SIlya Yanok #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 113bc8f8c26SIlya Yanok #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 114bc8f8c26SIlya Yanok #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 115bc8f8c26SIlya Yanok 116bc8f8c26SIlya Yanok /* 117bc8f8c26SIlya Yanok * DDR Setup 118bc8f8c26SIlya Yanok */ 119bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 120bc8f8c26SIlya Yanok #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 121bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 122bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 123bc8f8c26SIlya Yanok #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 124bc8f8c26SIlya Yanok | DDRCDR_PZ_LOZ \ 125bc8f8c26SIlya Yanok | DDRCDR_NZ_LOZ \ 126bc8f8c26SIlya Yanok | DDRCDR_ODT \ 127bc8f8c26SIlya Yanok | DDRCDR_Q_DRN) 128bc8f8c26SIlya Yanok /* 0x7b880001 */ 129bc8f8c26SIlya Yanok /* 130bc8f8c26SIlya Yanok * Manually set up DDR parameters 131bc8f8c26SIlya Yanok * consist of two chips HY5PS12621BFP-C4 from HYNIX 132bc8f8c26SIlya Yanok */ 133bc8f8c26SIlya Yanok 134bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 135bc8f8c26SIlya Yanok 136bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 137bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 1382fef4020SJoe Hershberger | CSCONFIG_ODT_RD_NEVER \ 1392fef4020SJoe Hershberger | CSCONFIG_ODT_WR_ONLY_CURRENT \ 1402fef4020SJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 1412fef4020SJoe Hershberger | CSCONFIG_COL_BIT_10) 142bc8f8c26SIlya Yanok /* 0x80010102 */ 143bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_TIMING_3 0x00000000 144bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 145bc8f8c26SIlya Yanok | (0 << TIMING_CFG0_WRT_SHIFT) \ 146bc8f8c26SIlya Yanok | (0 << TIMING_CFG0_RRT_SHIFT) \ 147bc8f8c26SIlya Yanok | (0 << TIMING_CFG0_WWT_SHIFT) \ 148bc8f8c26SIlya Yanok | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 149bc8f8c26SIlya Yanok | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 150bc8f8c26SIlya Yanok | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 151bc8f8c26SIlya Yanok | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 152bc8f8c26SIlya Yanok /* 0x00220802 */ 153bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 154bc8f8c26SIlya Yanok | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 155bc8f8c26SIlya Yanok | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 156bc8f8c26SIlya Yanok | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 157bc8f8c26SIlya Yanok | (6 << TIMING_CFG1_REFREC_SHIFT) \ 158bc8f8c26SIlya Yanok | (2 << TIMING_CFG1_WRREC_SHIFT) \ 159bc8f8c26SIlya Yanok | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 160bc8f8c26SIlya Yanok | (2 << TIMING_CFG1_WRTORD_SHIFT)) 161bc8f8c26SIlya Yanok /* 0x27256222 */ 162bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 163bc8f8c26SIlya Yanok | (4 << TIMING_CFG2_CPO_SHIFT) \ 164bc8f8c26SIlya Yanok | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 165bc8f8c26SIlya Yanok | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 166bc8f8c26SIlya Yanok | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 167bc8f8c26SIlya Yanok | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 168bc8f8c26SIlya Yanok | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 169bc8f8c26SIlya Yanok /* 0x121048c5 */ 170bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 171bc8f8c26SIlya Yanok | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 172bc8f8c26SIlya Yanok /* 0x03600100 */ 173bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 174bc8f8c26SIlya Yanok | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1752fef4020SJoe Hershberger | SDRAM_CFG_DBW_32) 176bc8f8c26SIlya Yanok /* 0x43080000 */ 177bc8f8c26SIlya Yanok 178bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 179bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 180bc8f8c26SIlya Yanok | (0x0232 << SDRAM_MODE_SD_SHIFT)) 181bc8f8c26SIlya Yanok /* ODT 150ohm CL=3, AL=1 on SDRAM */ 182bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_MODE2 0x00000000 183bc8f8c26SIlya Yanok 184bc8f8c26SIlya Yanok /* 185bc8f8c26SIlya Yanok * Memory test 186bc8f8c26SIlya Yanok */ 187bc8f8c26SIlya Yanok #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 188bc8f8c26SIlya Yanok #define CONFIG_SYS_MEMTEST_END 0x07f00000 189bc8f8c26SIlya Yanok 190bc8f8c26SIlya Yanok /* 191bc8f8c26SIlya Yanok * The reserved memory 192bc8f8c26SIlya Yanok */ 19314d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 194bc8f8c26SIlya Yanok 195bc8f8c26SIlya Yanok #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 196bc8f8c26SIlya Yanok #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 197bc8f8c26SIlya Yanok 198bc8f8c26SIlya Yanok /* 199bc8f8c26SIlya Yanok * Initial RAM Base Address Setup 200bc8f8c26SIlya Yanok */ 201bc8f8c26SIlya Yanok #define CONFIG_SYS_INIT_RAM_LOCK 1 202bc8f8c26SIlya Yanok #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 203553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 204bc8f8c26SIlya Yanok #define CONFIG_SYS_GBL_DATA_OFFSET \ 20525ddd1fbSWolfgang Denk (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 206bc8f8c26SIlya Yanok 207bc8f8c26SIlya Yanok /* 208bc8f8c26SIlya Yanok * Local Bus Configuration & Clock Setup 209bc8f8c26SIlya Yanok */ 210bc8f8c26SIlya Yanok #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 211bc8f8c26SIlya Yanok #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 212bc8f8c26SIlya Yanok #define CONFIG_SYS_LBC_LBCR 0x00040000 213bc8f8c26SIlya Yanok 214bc8f8c26SIlya Yanok /* 215bc8f8c26SIlya Yanok * FLASH on the Local Bus 216bc8f8c26SIlya Yanok */ 217bc8f8c26SIlya Yanok #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 218bc8f8c26SIlya Yanok 219bc8f8c26SIlya Yanok #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ 220bc8f8c26SIlya Yanok #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ 221bc8f8c26SIlya Yanok 222bc8f8c26SIlya Yanok /* Window base at flash base */ 223bc8f8c26SIlya Yanok #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 224bc8f8c26SIlya Yanok #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) 225bc8f8c26SIlya Yanok 2267d6a0982SJoe Hershberger #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 2277d6a0982SJoe Hershberger | BR_PS_16 /* 16 bit port */ \ 2287d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 22980ae4df9SJoe Hershberger | BR_V) /* valid */ 2307d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 231bc8f8c26SIlya Yanok | OR_UPM_XAM \ 232bc8f8c26SIlya Yanok | OR_GPCM_CSNT \ 233bc8f8c26SIlya Yanok | OR_GPCM_ACS_DIV2 \ 234bc8f8c26SIlya Yanok | OR_GPCM_XACS \ 235bc8f8c26SIlya Yanok | OR_GPCM_SCY_4 \ 2367d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2377d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET) 238bc8f8c26SIlya Yanok 239bc8f8c26SIlya Yanok #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 240bc8f8c26SIlya Yanok #define CONFIG_SYS_MAX_FLASH_SECT 512 241bc8f8c26SIlya Yanok 242bc8f8c26SIlya Yanok /* Flash Erase Timeout (ms) */ 243bc8f8c26SIlya Yanok #define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024) 244bc8f8c26SIlya Yanok /* Flash Write Timeout (ms) */ 245bc8f8c26SIlya Yanok #define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024) 246bc8f8c26SIlya Yanok 247bc8f8c26SIlya Yanok /* 248bc8f8c26SIlya Yanok * SJA1000 CAN controller on Local Bus 249bc8f8c26SIlya Yanok */ 250bc8f8c26SIlya Yanok #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 251bc8f8c26SIlya Yanok #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SJA1000_BASE \ 2527d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port size */ \ 2537d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 254bc8f8c26SIlya Yanok | BR_V) /* valid */ 2557d6a0982SJoe Hershberger #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 256bc8f8c26SIlya Yanok | OR_GPCM_SCY_5 \ 2577d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET) 258bc8f8c26SIlya Yanok /* 0xFFFF8052 */ 259bc8f8c26SIlya Yanok 260bc8f8c26SIlya Yanok #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE 261bc8f8c26SIlya Yanok #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 262bc8f8c26SIlya Yanok 263bc8f8c26SIlya Yanok /* 264bc8f8c26SIlya Yanok * CPLD on Local Bus 265bc8f8c26SIlya Yanok */ 266bc8f8c26SIlya Yanok #define CONFIG_SYS_CPLD_BASE 0xFBFF8000 267bc8f8c26SIlya Yanok #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_CPLD_BASE \ 2687d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 2697d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 270bc8f8c26SIlya Yanok | BR_V) /* valid */ 2717d6a0982SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \ 272bc8f8c26SIlya Yanok | OR_GPCM_SCY_4 \ 2737d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET) 274bc8f8c26SIlya Yanok /* 0xFFFF8042 */ 275bc8f8c26SIlya Yanok 276bc8f8c26SIlya Yanok #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE 277bc8f8c26SIlya Yanok #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 278bc8f8c26SIlya Yanok 279bc8f8c26SIlya Yanok /* 280bc8f8c26SIlya Yanok * Serial Port 281bc8f8c26SIlya Yanok */ 282bc8f8c26SIlya Yanok #undef CONFIG_SERIAL_SOFTWARE_FIFO 283bc8f8c26SIlya Yanok #define CONFIG_SYS_NS16550_SERIAL 284bc8f8c26SIlya Yanok #define CONFIG_SYS_NS16550_REG_SIZE 1 285bc8f8c26SIlya Yanok #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 286bc8f8c26SIlya Yanok 287bc8f8c26SIlya Yanok #define CONFIG_SYS_BAUDRATE_TABLE \ 288bc8f8c26SIlya Yanok {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 289bc8f8c26SIlya Yanok 290bc8f8c26SIlya Yanok #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 291bc8f8c26SIlya Yanok #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 292bc8f8c26SIlya Yanok 293bc8f8c26SIlya Yanok /* I2C */ 29400f792e0SHeiko Schocher #define CONFIG_SYS_I2C 29500f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 29600f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 29700f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 29800f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 29900f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 30000f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 30100f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 302bc8f8c26SIlya Yanok 303bc8f8c26SIlya Yanok /* 304bc8f8c26SIlya Yanok * General PCI 305bc8f8c26SIlya Yanok * Addresses are mapped 1-1. 306bc8f8c26SIlya Yanok */ 307bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_BASE 0xA0000000 308bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 309bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 310bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 311bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 312bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 313bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 314bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 315bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 316bc8f8c26SIlya Yanok 317bc8f8c26SIlya Yanok /* enable PCIE clock */ 318bc8f8c26SIlya Yanok #define CONFIG_SYS_SCCR_PCIEXP1CM 1 319bc8f8c26SIlya Yanok 320842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 321bc8f8c26SIlya Yanok #define CONFIG_PCIE 322bc8f8c26SIlya Yanok 323bc8f8c26SIlya Yanok #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 324bc8f8c26SIlya Yanok #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 325bc8f8c26SIlya Yanok 326bc8f8c26SIlya Yanok /* 327bc8f8c26SIlya Yanok * TSEC 328bc8f8c26SIlya Yanok */ 329bc8f8c26SIlya Yanok #define CONFIG_SYS_TSEC1_OFFSET 0x24000 330bc8f8c26SIlya Yanok #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 331bc8f8c26SIlya Yanok #define CONFIG_SYS_TSEC2_OFFSET 0x25000 332bc8f8c26SIlya Yanok #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 333bc8f8c26SIlya Yanok 334bc8f8c26SIlya Yanok /* 335bc8f8c26SIlya Yanok * TSEC ethernet configuration 336bc8f8c26SIlya Yanok */ 337bc8f8c26SIlya Yanok #define CONFIG_TSEC1_NAME "eTSEC0" 338bc8f8c26SIlya Yanok #define CONFIG_TSEC2_NAME "eTSEC1" 339bc8f8c26SIlya Yanok #define TSEC1_PHY_ADDR 1 340bc8f8c26SIlya Yanok #define TSEC2_PHY_ADDR 2 341bc8f8c26SIlya Yanok #define TSEC1_PHYIDX 0 342bc8f8c26SIlya Yanok #define TSEC2_PHYIDX 0 343bc8f8c26SIlya Yanok #define TSEC1_FLAGS 0 344bc8f8c26SIlya Yanok #define TSEC2_FLAGS 0 345bc8f8c26SIlya Yanok 346bc8f8c26SIlya Yanok /* Options are: eTSEC[0-1] */ 347bc8f8c26SIlya Yanok #define CONFIG_ETHPRIME "eTSEC0" 348bc8f8c26SIlya Yanok 349bc8f8c26SIlya Yanok /* 350bc8f8c26SIlya Yanok * Environment 351bc8f8c26SIlya Yanok */ 352bc8f8c26SIlya Yanok #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 353bc8f8c26SIlya Yanok CONFIG_SYS_MONITOR_LEN) 354bc8f8c26SIlya Yanok #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 355bc8f8c26SIlya Yanok #define CONFIG_ENV_SIZE 0x2000 356bc8f8c26SIlya Yanok #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 357bc8f8c26SIlya Yanok #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 358bc8f8c26SIlya Yanok 359bc8f8c26SIlya Yanok #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 360bc8f8c26SIlya Yanok #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 361bc8f8c26SIlya Yanok 362bc8f8c26SIlya Yanok /* 363bc8f8c26SIlya Yanok * BOOTP options 364bc8f8c26SIlya Yanok */ 365bc8f8c26SIlya Yanok #define CONFIG_BOOTP_BOOTFILESIZE 366bc8f8c26SIlya Yanok 367bc8f8c26SIlya Yanok /* 368bc8f8c26SIlya Yanok * Command line configuration. 369bc8f8c26SIlya Yanok */ 370bc8f8c26SIlya Yanok 371bc8f8c26SIlya Yanok /* 372bc8f8c26SIlya Yanok * Miscellaneous configurable options 373bc8f8c26SIlya Yanok */ 374bc8f8c26SIlya Yanok #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 375bc8f8c26SIlya Yanok 376bc8f8c26SIlya Yanok #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 377bc8f8c26SIlya Yanok 378bc8f8c26SIlya Yanok /* Boot Argument Buffer Size */ 379bc8f8c26SIlya Yanok #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 380bc8f8c26SIlya Yanok 381bc8f8c26SIlya Yanok /* 382bc8f8c26SIlya Yanok * For booting Linux, the board info and command line data 383bc8f8c26SIlya Yanok * have to be in the first 8 MB of memory, since this is 384bc8f8c26SIlya Yanok * the maximum mapped by the Linux kernel during initialization. 385bc8f8c26SIlya Yanok */ 3869eda770bSKim Phillips #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 387bc8f8c26SIlya Yanok 388bc8f8c26SIlya Yanok /* 389bc8f8c26SIlya Yanok * Core HID Setup 390bc8f8c26SIlya Yanok */ 391bc8f8c26SIlya Yanok #define CONFIG_SYS_HID0_INIT 0x000000000 392bc8f8c26SIlya Yanok #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 393bc8f8c26SIlya Yanok HID0_ENABLE_INSTRUCTION_CACHE | \ 394bc8f8c26SIlya Yanok HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 395bc8f8c26SIlya Yanok #define CONFIG_SYS_HID2 HID2_HBE 396bc8f8c26SIlya Yanok 397bc8f8c26SIlya Yanok /* 398bc8f8c26SIlya Yanok * MMU Setup 399bc8f8c26SIlya Yanok */ 400bc8f8c26SIlya Yanok 401bc8f8c26SIlya Yanok /* DDR: cache cacheable */ 40272cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 403bc8f8c26SIlya Yanok BATL_MEMCOHERENCE) 404bc8f8c26SIlya Yanok #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 405bc8f8c26SIlya Yanok BATU_VS | BATU_VP) 406bc8f8c26SIlya Yanok #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 407bc8f8c26SIlya Yanok #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 408bc8f8c26SIlya Yanok 409bc8f8c26SIlya Yanok /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 41072cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 411bc8f8c26SIlya Yanok BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 412bc8f8c26SIlya Yanok #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 413bc8f8c26SIlya Yanok BATU_VP) 414bc8f8c26SIlya Yanok #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 415bc8f8c26SIlya Yanok #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 416bc8f8c26SIlya Yanok 417bc8f8c26SIlya Yanok /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 41872cd4087SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 419bc8f8c26SIlya Yanok BATL_MEMCOHERENCE) 420bc8f8c26SIlya Yanok #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 421bc8f8c26SIlya Yanok BATU_VS | BATU_VP) 42272cd4087SJoe Hershberger #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 423bc8f8c26SIlya Yanok BATL_CACHEINHIBIT | \ 424bc8f8c26SIlya Yanok BATL_GUARDEDSTORAGE) 425bc8f8c26SIlya Yanok #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 426bc8f8c26SIlya Yanok 427bc8f8c26SIlya Yanok /* Stack in dcache: cacheable, no memory coherence */ 42872cd4087SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 429bc8f8c26SIlya Yanok #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 430bc8f8c26SIlya Yanok BATU_VS | BATU_VP) 431bc8f8c26SIlya Yanok #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 432bc8f8c26SIlya Yanok #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 433bc8f8c26SIlya Yanok 434bc8f8c26SIlya Yanok /* 435bc8f8c26SIlya Yanok * Environment Configuration 436bc8f8c26SIlya Yanok */ 437bc8f8c26SIlya Yanok 438bc8f8c26SIlya Yanok #define CONFIG_ENV_OVERWRITE 439bc8f8c26SIlya Yanok 440bc8f8c26SIlya Yanok #if defined(CONFIG_TSEC_ENET) 441bc8f8c26SIlya Yanok #define CONFIG_HAS_ETH0 442bc8f8c26SIlya Yanok #define CONFIG_HAS_ETH1 443bc8f8c26SIlya Yanok #endif 444bc8f8c26SIlya Yanok 445bc8f8c26SIlya Yanok #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 446bc8f8c26SIlya Yanok 447bc8f8c26SIlya Yanok 448bc8f8c26SIlya Yanok #define CONFIG_EXTRA_ENV_SETTINGS \ 449bc8f8c26SIlya Yanok "netdev=eth0\0" \ 450bc8f8c26SIlya Yanok "consoledev=ttyS0\0" \ 451bc8f8c26SIlya Yanok "nfsargs=setenv bootargs root=/dev/nfs rw " \ 452bc8f8c26SIlya Yanok "nfsroot=${serverip}:${rootpath}\0" \ 453bc8f8c26SIlya Yanok "ramargs=setenv bootargs root=/dev/ram rw\0" \ 454bc8f8c26SIlya Yanok "addip=setenv bootargs ${bootargs} " \ 455bc8f8c26SIlya Yanok "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 456bc8f8c26SIlya Yanok ":${hostname}:${netdev}:off panic=1\0" \ 457bc8f8c26SIlya Yanok "addtty=setenv bootargs ${bootargs}" \ 458bc8f8c26SIlya Yanok " console=${consoledev},${baudrate}\0" \ 459bc8f8c26SIlya Yanok "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 460bc8f8c26SIlya Yanok "addmisc=setenv bootargs ${bootargs}\0" \ 461bc8f8c26SIlya Yanok "kernel_addr=FC0A0000\0" \ 462bc8f8c26SIlya Yanok "fdt_addr=FC2A0000\0" \ 463bc8f8c26SIlya Yanok "ramdisk_addr=FC2C0000\0" \ 464bc8f8c26SIlya Yanok "u-boot=mpc8308_p1m/u-boot.bin\0" \ 465bc8f8c26SIlya Yanok "kernel_addr_r=1000000\0" \ 466bc8f8c26SIlya Yanok "fdt_addr_r=C00000\0" \ 467bc8f8c26SIlya Yanok "hostname=mpc8308_p1m\0" \ 468bc8f8c26SIlya Yanok "bootfile=mpc8308_p1m/uImage\0" \ 469bc8f8c26SIlya Yanok "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \ 470bc8f8c26SIlya Yanok "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 471bc8f8c26SIlya Yanok "flash_self=run ramargs addip addtty addmtd addmisc;" \ 472bc8f8c26SIlya Yanok "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 473bc8f8c26SIlya Yanok "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 474bc8f8c26SIlya Yanok "bootm ${kernel_addr} - ${fdt_addr}\0" \ 475bc8f8c26SIlya Yanok "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 476bc8f8c26SIlya Yanok "tftp ${fdt_addr_r} ${fdtfile};" \ 477bc8f8c26SIlya Yanok "run nfsargs addip addtty addmtd addmisc;" \ 478bc8f8c26SIlya Yanok "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 479bc8f8c26SIlya Yanok "bootcmd=run flash_self\0" \ 480bc8f8c26SIlya Yanok "load=tftp ${loadaddr} ${u-boot}\0" \ 48193ea89f0SMarek Vasut "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 48293ea89f0SMarek Vasut " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 483bc8f8c26SIlya Yanok " +${filesize};cp.b ${fileaddr} " \ 48493ea89f0SMarek Vasut __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 485bc8f8c26SIlya Yanok "upd=run load update\0" \ 486bc8f8c26SIlya Yanok 487bc8f8c26SIlya Yanok #endif /* __CONFIG_H */ 488