1bc8f8c26SIlya Yanok /* 2bc8f8c26SIlya Yanok * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 3bc8f8c26SIlya Yanok * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4bc8f8c26SIlya Yanok * 5bc8f8c26SIlya Yanok * 6bc8f8c26SIlya Yanok * See file CREDITS for list of people who contributed to this 7bc8f8c26SIlya Yanok * project. 8bc8f8c26SIlya Yanok * 9bc8f8c26SIlya Yanok * This program is free software; you can redistribute it and/or 10bc8f8c26SIlya Yanok * modify it under the terms of the GNU General Public License as 11bc8f8c26SIlya Yanok * published by the Free Software Foundation; either version 2 of 12bc8f8c26SIlya Yanok * the License, or (at your option) any later version. 13bc8f8c26SIlya Yanok * 14bc8f8c26SIlya Yanok * This program is distributed in the hope that it will be useful, 15bc8f8c26SIlya Yanok * but WITHOUT ANY WARRANTY; without even the implied warranty of 16bc8f8c26SIlya Yanok * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17bc8f8c26SIlya Yanok * GNU General Public License for more details. 18bc8f8c26SIlya Yanok * 19bc8f8c26SIlya Yanok * You should have received a copy of the GNU General Public License 20bc8f8c26SIlya Yanok * along with this program; if not, write to the Free Software 21bc8f8c26SIlya Yanok * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22bc8f8c26SIlya Yanok * MA 02111-1307 USA 23bc8f8c26SIlya Yanok */ 24bc8f8c26SIlya Yanok 25bc8f8c26SIlya Yanok #ifndef __CONFIG_H 26bc8f8c26SIlya Yanok #define __CONFIG_H 27bc8f8c26SIlya Yanok 28bc8f8c26SIlya Yanok /* 29bc8f8c26SIlya Yanok * High Level Configuration Options 30bc8f8c26SIlya Yanok */ 31bc8f8c26SIlya Yanok #define CONFIG_E300 1 /* E300 family */ 32bc8f8c26SIlya Yanok #define CONFIG_MPC83xx 1 /* MPC83xx family */ 33bc8f8c26SIlya Yanok #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 34bc8f8c26SIlya Yanok #define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */ 35bc8f8c26SIlya Yanok 362ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 372ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFC000000 382ae18241SWolfgang Denk #endif 392ae18241SWolfgang Denk 40bc8f8c26SIlya Yanok /* 41bc8f8c26SIlya Yanok * On-board devices 42bc8f8c26SIlya Yanok * 43bc8f8c26SIlya Yanok * TSECs 44bc8f8c26SIlya Yanok */ 45bc8f8c26SIlya Yanok #define CONFIG_TSEC1 46bc8f8c26SIlya Yanok #define CONFIG_TSEC2 47bc8f8c26SIlya Yanok 48bc8f8c26SIlya Yanok /* 49bc8f8c26SIlya Yanok * System Clock Setup 50bc8f8c26SIlya Yanok */ 51bc8f8c26SIlya Yanok #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 52bc8f8c26SIlya Yanok #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 53bc8f8c26SIlya Yanok 54bc8f8c26SIlya Yanok /* 55bc8f8c26SIlya Yanok * Hardware Reset Configuration Word 56bc8f8c26SIlya Yanok * if CLKIN is 66.66MHz, then 57bc8f8c26SIlya Yanok * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 58bc8f8c26SIlya Yanok * We choose the A type silicon as default, so the core is 400Mhz. 59bc8f8c26SIlya Yanok */ 60bc8f8c26SIlya Yanok #define CONFIG_SYS_HRCW_LOW (\ 61bc8f8c26SIlya Yanok HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 62bc8f8c26SIlya Yanok HRCWL_DDR_TO_SCB_CLK_2X1 |\ 63bc8f8c26SIlya Yanok HRCWL_SVCOD_DIV_2 |\ 64bc8f8c26SIlya Yanok HRCWL_CSB_TO_CLKIN_4X1 |\ 65bc8f8c26SIlya Yanok HRCWL_CORE_TO_CSB_3X1) 66bc8f8c26SIlya Yanok /* 67bc8f8c26SIlya Yanok * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 68bc8f8c26SIlya Yanok * in 8308's HRCWH according to the manual, but original Freescale's 69bc8f8c26SIlya Yanok * code has them and I've expirienced some problems using the board 70bc8f8c26SIlya Yanok * with BDI3000 attached when I've tried to set these bits to zero 71bc8f8c26SIlya Yanok * (UART doesn't work after the 'reset run' command). 72bc8f8c26SIlya Yanok */ 73bc8f8c26SIlya Yanok #define CONFIG_SYS_HRCW_HIGH (\ 74bc8f8c26SIlya Yanok HRCWH_PCI_HOST |\ 75bc8f8c26SIlya Yanok HRCWH_PCI1_ARBITER_ENABLE |\ 76bc8f8c26SIlya Yanok HRCWH_CORE_ENABLE |\ 77bc8f8c26SIlya Yanok HRCWH_FROM_0X00000100 |\ 78bc8f8c26SIlya Yanok HRCWH_BOOTSEQ_DISABLE |\ 79bc8f8c26SIlya Yanok HRCWH_SW_WATCHDOG_DISABLE |\ 80bc8f8c26SIlya Yanok HRCWH_ROM_LOC_LOCAL_16BIT |\ 81bc8f8c26SIlya Yanok HRCWH_RL_EXT_LEGACY |\ 82bc8f8c26SIlya Yanok HRCWH_TSEC1M_IN_MII |\ 83bc8f8c26SIlya Yanok HRCWH_TSEC2M_IN_MII |\ 84bc8f8c26SIlya Yanok HRCWH_BIG_ENDIAN) 85bc8f8c26SIlya Yanok 86bc8f8c26SIlya Yanok /* 87bc8f8c26SIlya Yanok * System IO Config 88bc8f8c26SIlya Yanok */ 89bc8f8c26SIlya Yanok #define CONFIG_SYS_SICRH (\ 90bc8f8c26SIlya Yanok SICRH_ESDHC_A_GPIO |\ 91bc8f8c26SIlya Yanok SICRH_ESDHC_B_GPIO |\ 92bc8f8c26SIlya Yanok SICRH_ESDHC_C_GTM |\ 93bc8f8c26SIlya Yanok SICRH_GPIO_A_TSEC2 |\ 94bc8f8c26SIlya Yanok SICRH_GPIO_B_TSEC2_TX_CLK |\ 95bc8f8c26SIlya Yanok SICRH_IEEE1588_A_GPIO |\ 96bc8f8c26SIlya Yanok SICRH_USB |\ 97bc8f8c26SIlya Yanok SICRH_GTM_GPIO |\ 98bc8f8c26SIlya Yanok SICRH_IEEE1588_B_GPIO |\ 99bc8f8c26SIlya Yanok SICRH_ETSEC2_CRS |\ 100bc8f8c26SIlya Yanok SICRH_GPIOSEL_1 |\ 101bc8f8c26SIlya Yanok SICRH_TMROBI_V3P3 |\ 102bc8f8c26SIlya Yanok SICRH_TSOBI1_V3P3 |\ 103bc8f8c26SIlya Yanok SICRH_TSOBI2_V3P3) /* 0xf577d100 */ 104bc8f8c26SIlya Yanok #define CONFIG_SYS_SICRL (\ 105bc8f8c26SIlya Yanok SICRL_SPI_PF0 |\ 106bc8f8c26SIlya Yanok SICRL_UART_PF0 |\ 107bc8f8c26SIlya Yanok SICRL_IRQ_PF0 |\ 108bc8f8c26SIlya Yanok SICRL_I2C2_PF0 |\ 109bc8f8c26SIlya Yanok SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ 110bc8f8c26SIlya Yanok 111bc8f8c26SIlya Yanok #define CONFIG_SYS_GPIO1_PRELIM 112bc8f8c26SIlya Yanok /* GPIO Default input/output settings */ 113bc8f8c26SIlya Yanok #define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00 114bc8f8c26SIlya Yanok /* 115bc8f8c26SIlya Yanok * Default GPIO values: 116bc8f8c26SIlya Yanok * LED#1 enabled; WLAN enabled; Both COM LED on (orange) 117bc8f8c26SIlya Yanok */ 118bc8f8c26SIlya Yanok #define CONFIG_SYS_GPIO1_DAT 0x08008C00 119bc8f8c26SIlya Yanok 120bc8f8c26SIlya Yanok /* 121bc8f8c26SIlya Yanok * IMMR new address 122bc8f8c26SIlya Yanok */ 123bc8f8c26SIlya Yanok #define CONFIG_SYS_IMMR 0xE0000000 124bc8f8c26SIlya Yanok 125bc8f8c26SIlya Yanok /* 126bc8f8c26SIlya Yanok * SERDES 127bc8f8c26SIlya Yanok */ 128bc8f8c26SIlya Yanok #define CONFIG_FSL_SERDES 129bc8f8c26SIlya Yanok #define CONFIG_FSL_SERDES1 0xe3000 130bc8f8c26SIlya Yanok 131bc8f8c26SIlya Yanok /* 132bc8f8c26SIlya Yanok * Arbiter Setup 133bc8f8c26SIlya Yanok */ 134bc8f8c26SIlya Yanok #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 135bc8f8c26SIlya Yanok #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 136bc8f8c26SIlya Yanok #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 137bc8f8c26SIlya Yanok 138bc8f8c26SIlya Yanok /* 139bc8f8c26SIlya Yanok * DDR Setup 140bc8f8c26SIlya Yanok */ 141bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 142bc8f8c26SIlya Yanok #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 143bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 144bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 145bc8f8c26SIlya Yanok #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 146bc8f8c26SIlya Yanok | DDRCDR_PZ_LOZ \ 147bc8f8c26SIlya Yanok | DDRCDR_NZ_LOZ \ 148bc8f8c26SIlya Yanok | DDRCDR_ODT \ 149bc8f8c26SIlya Yanok | DDRCDR_Q_DRN) 150bc8f8c26SIlya Yanok /* 0x7b880001 */ 151bc8f8c26SIlya Yanok /* 152bc8f8c26SIlya Yanok * Manually set up DDR parameters 153bc8f8c26SIlya Yanok * consist of two chips HY5PS12621BFP-C4 from HYNIX 154bc8f8c26SIlya Yanok */ 155bc8f8c26SIlya Yanok 156bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 157bc8f8c26SIlya Yanok 158bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 159bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 1602fef4020SJoe Hershberger | CSCONFIG_ODT_RD_NEVER \ 1612fef4020SJoe Hershberger | CSCONFIG_ODT_WR_ONLY_CURRENT \ 1622fef4020SJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 1632fef4020SJoe Hershberger | CSCONFIG_COL_BIT_10) 164bc8f8c26SIlya Yanok /* 0x80010102 */ 165bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_TIMING_3 0x00000000 166bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 167bc8f8c26SIlya Yanok | (0 << TIMING_CFG0_WRT_SHIFT) \ 168bc8f8c26SIlya Yanok | (0 << TIMING_CFG0_RRT_SHIFT) \ 169bc8f8c26SIlya Yanok | (0 << TIMING_CFG0_WWT_SHIFT) \ 170bc8f8c26SIlya Yanok | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 171bc8f8c26SIlya Yanok | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 172bc8f8c26SIlya Yanok | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 173bc8f8c26SIlya Yanok | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 174bc8f8c26SIlya Yanok /* 0x00220802 */ 175bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 176bc8f8c26SIlya Yanok | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 177bc8f8c26SIlya Yanok | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 178bc8f8c26SIlya Yanok | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 179bc8f8c26SIlya Yanok | (6 << TIMING_CFG1_REFREC_SHIFT) \ 180bc8f8c26SIlya Yanok | (2 << TIMING_CFG1_WRREC_SHIFT) \ 181bc8f8c26SIlya Yanok | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 182bc8f8c26SIlya Yanok | (2 << TIMING_CFG1_WRTORD_SHIFT)) 183bc8f8c26SIlya Yanok /* 0x27256222 */ 184bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 185bc8f8c26SIlya Yanok | (4 << TIMING_CFG2_CPO_SHIFT) \ 186bc8f8c26SIlya Yanok | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 187bc8f8c26SIlya Yanok | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 188bc8f8c26SIlya Yanok | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 189bc8f8c26SIlya Yanok | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 190bc8f8c26SIlya Yanok | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 191bc8f8c26SIlya Yanok /* 0x121048c5 */ 192bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 193bc8f8c26SIlya Yanok | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 194bc8f8c26SIlya Yanok /* 0x03600100 */ 195bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 196bc8f8c26SIlya Yanok | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1972fef4020SJoe Hershberger | SDRAM_CFG_DBW_32) 198bc8f8c26SIlya Yanok /* 0x43080000 */ 199bc8f8c26SIlya Yanok 200bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 201bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 202bc8f8c26SIlya Yanok | (0x0232 << SDRAM_MODE_SD_SHIFT)) 203bc8f8c26SIlya Yanok /* ODT 150ohm CL=3, AL=1 on SDRAM */ 204bc8f8c26SIlya Yanok #define CONFIG_SYS_DDR_MODE2 0x00000000 205bc8f8c26SIlya Yanok 206bc8f8c26SIlya Yanok /* 207bc8f8c26SIlya Yanok * Memory test 208bc8f8c26SIlya Yanok */ 209bc8f8c26SIlya Yanok #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 210bc8f8c26SIlya Yanok #define CONFIG_SYS_MEMTEST_END 0x07f00000 211bc8f8c26SIlya Yanok 212bc8f8c26SIlya Yanok /* 213bc8f8c26SIlya Yanok * The reserved memory 214bc8f8c26SIlya Yanok */ 21514d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 216bc8f8c26SIlya Yanok 217bc8f8c26SIlya Yanok #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 218bc8f8c26SIlya Yanok #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 219bc8f8c26SIlya Yanok 220bc8f8c26SIlya Yanok /* 221bc8f8c26SIlya Yanok * Initial RAM Base Address Setup 222bc8f8c26SIlya Yanok */ 223bc8f8c26SIlya Yanok #define CONFIG_SYS_INIT_RAM_LOCK 1 224bc8f8c26SIlya Yanok #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 225553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 226bc8f8c26SIlya Yanok #define CONFIG_SYS_GBL_DATA_OFFSET \ 22725ddd1fbSWolfgang Denk (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 228bc8f8c26SIlya Yanok 229bc8f8c26SIlya Yanok /* 230bc8f8c26SIlya Yanok * Local Bus Configuration & Clock Setup 231bc8f8c26SIlya Yanok */ 232bc8f8c26SIlya Yanok #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 233bc8f8c26SIlya Yanok #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 234bc8f8c26SIlya Yanok #define CONFIG_SYS_LBC_LBCR 0x00040000 235bc8f8c26SIlya Yanok 236bc8f8c26SIlya Yanok /* 237bc8f8c26SIlya Yanok * FLASH on the Local Bus 238bc8f8c26SIlya Yanok */ 239bc8f8c26SIlya Yanok #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 240bc8f8c26SIlya Yanok #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 241bc8f8c26SIlya Yanok #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 242bc8f8c26SIlya Yanok 243bc8f8c26SIlya Yanok #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ 244bc8f8c26SIlya Yanok #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ 245bc8f8c26SIlya Yanok #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 246bc8f8c26SIlya Yanok 247bc8f8c26SIlya Yanok /* Window base at flash base */ 248bc8f8c26SIlya Yanok #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 249bc8f8c26SIlya Yanok #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) 250bc8f8c26SIlya Yanok 251*7d6a0982SJoe Hershberger #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 252*7d6a0982SJoe Hershberger | BR_PS_16 /* 16 bit port */ \ 253*7d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 25480ae4df9SJoe Hershberger | BR_V) /* valid */ 255*7d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 256bc8f8c26SIlya Yanok | OR_UPM_XAM \ 257bc8f8c26SIlya Yanok | OR_GPCM_CSNT \ 258bc8f8c26SIlya Yanok | OR_GPCM_ACS_DIV2 \ 259bc8f8c26SIlya Yanok | OR_GPCM_XACS \ 260bc8f8c26SIlya Yanok | OR_GPCM_SCY_4 \ 261*7d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 262*7d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET) 263bc8f8c26SIlya Yanok 264bc8f8c26SIlya Yanok #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 265bc8f8c26SIlya Yanok #define CONFIG_SYS_MAX_FLASH_SECT 512 266bc8f8c26SIlya Yanok 267bc8f8c26SIlya Yanok /* Flash Erase Timeout (ms) */ 268bc8f8c26SIlya Yanok #define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024) 269bc8f8c26SIlya Yanok /* Flash Write Timeout (ms) */ 270bc8f8c26SIlya Yanok #define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024) 271bc8f8c26SIlya Yanok 272bc8f8c26SIlya Yanok /* 273bc8f8c26SIlya Yanok * SJA1000 CAN controller on Local Bus 274bc8f8c26SIlya Yanok */ 275bc8f8c26SIlya Yanok #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 276bc8f8c26SIlya Yanok #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SJA1000_BASE \ 277*7d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port size */ \ 278*7d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 279bc8f8c26SIlya Yanok | BR_V) /* valid */ 280*7d6a0982SJoe Hershberger #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 281bc8f8c26SIlya Yanok | OR_GPCM_SCY_5 \ 282*7d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET) 283bc8f8c26SIlya Yanok /* 0xFFFF8052 */ 284bc8f8c26SIlya Yanok 285bc8f8c26SIlya Yanok #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE 286bc8f8c26SIlya Yanok #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 287bc8f8c26SIlya Yanok 288bc8f8c26SIlya Yanok /* 289bc8f8c26SIlya Yanok * CPLD on Local Bus 290bc8f8c26SIlya Yanok */ 291bc8f8c26SIlya Yanok #define CONFIG_SYS_CPLD_BASE 0xFBFF8000 292bc8f8c26SIlya Yanok #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_CPLD_BASE \ 293*7d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 294*7d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 295bc8f8c26SIlya Yanok | BR_V) /* valid */ 296*7d6a0982SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \ 297bc8f8c26SIlya Yanok | OR_GPCM_SCY_4 \ 298*7d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET) 299bc8f8c26SIlya Yanok /* 0xFFFF8042 */ 300bc8f8c26SIlya Yanok 301bc8f8c26SIlya Yanok #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE 302bc8f8c26SIlya Yanok #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 303bc8f8c26SIlya Yanok 304bc8f8c26SIlya Yanok /* 305bc8f8c26SIlya Yanok * Serial Port 306bc8f8c26SIlya Yanok */ 307bc8f8c26SIlya Yanok #define CONFIG_CONS_INDEX 1 308bc8f8c26SIlya Yanok #undef CONFIG_SERIAL_SOFTWARE_FIFO 309bc8f8c26SIlya Yanok #define CONFIG_SYS_NS16550 310bc8f8c26SIlya Yanok #define CONFIG_SYS_NS16550_SERIAL 311bc8f8c26SIlya Yanok #define CONFIG_SYS_NS16550_REG_SIZE 1 312bc8f8c26SIlya Yanok #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 313bc8f8c26SIlya Yanok 314bc8f8c26SIlya Yanok #define CONFIG_SYS_BAUDRATE_TABLE \ 315bc8f8c26SIlya Yanok {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 316bc8f8c26SIlya Yanok 317bc8f8c26SIlya Yanok #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 318bc8f8c26SIlya Yanok #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 319bc8f8c26SIlya Yanok 320bc8f8c26SIlya Yanok /* Use the HUSH parser */ 321bc8f8c26SIlya Yanok #define CONFIG_SYS_HUSH_PARSER 322bc8f8c26SIlya Yanok #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 323bc8f8c26SIlya Yanok 324bc8f8c26SIlya Yanok /* Pass open firmware flat tree */ 325bc8f8c26SIlya Yanok #define CONFIG_OF_LIBFDT 1 326bc8f8c26SIlya Yanok #define CONFIG_OF_BOARD_SETUP 1 327bc8f8c26SIlya Yanok #define CONFIG_OF_STDOUT_VIA_ALIAS 1 328bc8f8c26SIlya Yanok 329bc8f8c26SIlya Yanok /* I2C */ 330bc8f8c26SIlya Yanok #define CONFIG_HARD_I2C /* I2C with hardware support */ 331bc8f8c26SIlya Yanok #define CONFIG_FSL_I2C 332bc8f8c26SIlya Yanok #define CONFIG_I2C_MULTI_BUS 333bc8f8c26SIlya Yanok #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 334bc8f8c26SIlya Yanok #define CONFIG_SYS_I2C_SLAVE 0x7F 335bc8f8c26SIlya Yanok #define CONFIG_SYS_I2C_OFFSET 0x3000 336bc8f8c26SIlya Yanok #define CONFIG_SYS_I2C2_OFFSET 0x3100 337bc8f8c26SIlya Yanok 338bc8f8c26SIlya Yanok /* 339bc8f8c26SIlya Yanok * General PCI 340bc8f8c26SIlya Yanok * Addresses are mapped 1-1. 341bc8f8c26SIlya Yanok */ 342bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_BASE 0xA0000000 343bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 344bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 345bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 346bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 347bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 348bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 349bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 350bc8f8c26SIlya Yanok #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 351bc8f8c26SIlya Yanok 352bc8f8c26SIlya Yanok /* enable PCIE clock */ 353bc8f8c26SIlya Yanok #define CONFIG_SYS_SCCR_PCIEXP1CM 1 354bc8f8c26SIlya Yanok 355bc8f8c26SIlya Yanok #define CONFIG_PCI 356bc8f8c26SIlya Yanok #define CONFIG_PCIE 357bc8f8c26SIlya Yanok 358bc8f8c26SIlya Yanok #define CONFIG_PCI_PNP /* do pci plug-and-play */ 359bc8f8c26SIlya Yanok 360bc8f8c26SIlya Yanok #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 361bc8f8c26SIlya Yanok #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 362bc8f8c26SIlya Yanok 363bc8f8c26SIlya Yanok /* 364bc8f8c26SIlya Yanok * TSEC 365bc8f8c26SIlya Yanok */ 366bc8f8c26SIlya Yanok #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 367bc8f8c26SIlya Yanok #define CONFIG_SYS_TSEC1_OFFSET 0x24000 368bc8f8c26SIlya Yanok #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 369bc8f8c26SIlya Yanok #define CONFIG_SYS_TSEC2_OFFSET 0x25000 370bc8f8c26SIlya Yanok #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 371bc8f8c26SIlya Yanok 372bc8f8c26SIlya Yanok /* 373bc8f8c26SIlya Yanok * TSEC ethernet configuration 374bc8f8c26SIlya Yanok */ 375bc8f8c26SIlya Yanok #define CONFIG_MII 1 /* MII PHY management */ 376bc8f8c26SIlya Yanok #define CONFIG_TSEC1_NAME "eTSEC0" 377bc8f8c26SIlya Yanok #define CONFIG_TSEC2_NAME "eTSEC1" 378bc8f8c26SIlya Yanok #define TSEC1_PHY_ADDR 1 379bc8f8c26SIlya Yanok #define TSEC2_PHY_ADDR 2 380bc8f8c26SIlya Yanok #define TSEC1_PHYIDX 0 381bc8f8c26SIlya Yanok #define TSEC2_PHYIDX 0 382bc8f8c26SIlya Yanok #define TSEC1_FLAGS 0 383bc8f8c26SIlya Yanok #define TSEC2_FLAGS 0 384bc8f8c26SIlya Yanok 385bc8f8c26SIlya Yanok /* Options are: eTSEC[0-1] */ 386bc8f8c26SIlya Yanok #define CONFIG_ETHPRIME "eTSEC0" 387bc8f8c26SIlya Yanok 388bc8f8c26SIlya Yanok /* 389bc8f8c26SIlya Yanok * Environment 390bc8f8c26SIlya Yanok */ 391bc8f8c26SIlya Yanok #define CONFIG_ENV_IS_IN_FLASH 1 392bc8f8c26SIlya Yanok #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 393bc8f8c26SIlya Yanok CONFIG_SYS_MONITOR_LEN) 394bc8f8c26SIlya Yanok #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 395bc8f8c26SIlya Yanok #define CONFIG_ENV_SIZE 0x2000 396bc8f8c26SIlya Yanok #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 397bc8f8c26SIlya Yanok #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 398bc8f8c26SIlya Yanok 399bc8f8c26SIlya Yanok #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 400bc8f8c26SIlya Yanok #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 401bc8f8c26SIlya Yanok 402bc8f8c26SIlya Yanok /* 403bc8f8c26SIlya Yanok * BOOTP options 404bc8f8c26SIlya Yanok */ 405bc8f8c26SIlya Yanok #define CONFIG_BOOTP_BOOTFILESIZE 406bc8f8c26SIlya Yanok #define CONFIG_BOOTP_BOOTPATH 407bc8f8c26SIlya Yanok #define CONFIG_BOOTP_GATEWAY 408bc8f8c26SIlya Yanok #define CONFIG_BOOTP_HOSTNAME 409bc8f8c26SIlya Yanok 410bc8f8c26SIlya Yanok /* 411bc8f8c26SIlya Yanok * Command line configuration. 412bc8f8c26SIlya Yanok */ 413bc8f8c26SIlya Yanok #include <config_cmd_default.h> 414bc8f8c26SIlya Yanok 415bc8f8c26SIlya Yanok #define CONFIG_CMD_DHCP 416bc8f8c26SIlya Yanok #define CONFIG_CMD_I2C 417bc8f8c26SIlya Yanok #define CONFIG_CMD_MII 418bc8f8c26SIlya Yanok #define CONFIG_CMD_NET 419bc8f8c26SIlya Yanok #define CONFIG_CMD_PCI 420bc8f8c26SIlya Yanok #define CONFIG_CMD_PING 421bc8f8c26SIlya Yanok 422bc8f8c26SIlya Yanok #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 423bc8f8c26SIlya Yanok 424bc8f8c26SIlya Yanok /* 425bc8f8c26SIlya Yanok * Miscellaneous configurable options 426bc8f8c26SIlya Yanok */ 427bc8f8c26SIlya Yanok #define CONFIG_SYS_LONGHELP /* undef to save memory */ 428bc8f8c26SIlya Yanok #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 429bc8f8c26SIlya Yanok #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 430bc8f8c26SIlya Yanok 431bc8f8c26SIlya Yanok #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 432bc8f8c26SIlya Yanok 433bc8f8c26SIlya Yanok /* Print Buffer Size */ 434bc8f8c26SIlya Yanok #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 435bc8f8c26SIlya Yanok #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 436bc8f8c26SIlya Yanok /* Boot Argument Buffer Size */ 437bc8f8c26SIlya Yanok #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 438bc8f8c26SIlya Yanok #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 439bc8f8c26SIlya Yanok 440bc8f8c26SIlya Yanok /* 441bc8f8c26SIlya Yanok * For booting Linux, the board info and command line data 442bc8f8c26SIlya Yanok * have to be in the first 8 MB of memory, since this is 443bc8f8c26SIlya Yanok * the maximum mapped by the Linux kernel during initialization. 444bc8f8c26SIlya Yanok */ 4459eda770bSKim Phillips #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 446bc8f8c26SIlya Yanok 447bc8f8c26SIlya Yanok /* 448bc8f8c26SIlya Yanok * Core HID Setup 449bc8f8c26SIlya Yanok */ 450bc8f8c26SIlya Yanok #define CONFIG_SYS_HID0_INIT 0x000000000 451bc8f8c26SIlya Yanok #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 452bc8f8c26SIlya Yanok HID0_ENABLE_INSTRUCTION_CACHE | \ 453bc8f8c26SIlya Yanok HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 454bc8f8c26SIlya Yanok #define CONFIG_SYS_HID2 HID2_HBE 455bc8f8c26SIlya Yanok 456bc8f8c26SIlya Yanok /* 457bc8f8c26SIlya Yanok * MMU Setup 458bc8f8c26SIlya Yanok */ 459bc8f8c26SIlya Yanok 460bc8f8c26SIlya Yanok /* DDR: cache cacheable */ 46172cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 462bc8f8c26SIlya Yanok BATL_MEMCOHERENCE) 463bc8f8c26SIlya Yanok #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 464bc8f8c26SIlya Yanok BATU_VS | BATU_VP) 465bc8f8c26SIlya Yanok #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 466bc8f8c26SIlya Yanok #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 467bc8f8c26SIlya Yanok 468bc8f8c26SIlya Yanok /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 46972cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 470bc8f8c26SIlya Yanok BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 471bc8f8c26SIlya Yanok #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 472bc8f8c26SIlya Yanok BATU_VP) 473bc8f8c26SIlya Yanok #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 474bc8f8c26SIlya Yanok #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 475bc8f8c26SIlya Yanok 476bc8f8c26SIlya Yanok /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 47772cd4087SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 478bc8f8c26SIlya Yanok BATL_MEMCOHERENCE) 479bc8f8c26SIlya Yanok #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 480bc8f8c26SIlya Yanok BATU_VS | BATU_VP) 48172cd4087SJoe Hershberger #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 482bc8f8c26SIlya Yanok BATL_CACHEINHIBIT | \ 483bc8f8c26SIlya Yanok BATL_GUARDEDSTORAGE) 484bc8f8c26SIlya Yanok #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 485bc8f8c26SIlya Yanok 486bc8f8c26SIlya Yanok /* Stack in dcache: cacheable, no memory coherence */ 48772cd4087SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 488bc8f8c26SIlya Yanok #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 489bc8f8c26SIlya Yanok BATU_VS | BATU_VP) 490bc8f8c26SIlya Yanok #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 491bc8f8c26SIlya Yanok #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 492bc8f8c26SIlya Yanok 493bc8f8c26SIlya Yanok /* 494bc8f8c26SIlya Yanok * Environment Configuration 495bc8f8c26SIlya Yanok */ 496bc8f8c26SIlya Yanok 497bc8f8c26SIlya Yanok #define CONFIG_ENV_OVERWRITE 498bc8f8c26SIlya Yanok 499bc8f8c26SIlya Yanok #if defined(CONFIG_TSEC_ENET) 500bc8f8c26SIlya Yanok #define CONFIG_HAS_ETH0 501bc8f8c26SIlya Yanok #define CONFIG_HAS_ETH1 502bc8f8c26SIlya Yanok #endif 503bc8f8c26SIlya Yanok 504bc8f8c26SIlya Yanok #define CONFIG_BAUDRATE 115200 505bc8f8c26SIlya Yanok 506bc8f8c26SIlya Yanok #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 507bc8f8c26SIlya Yanok 508bc8f8c26SIlya Yanok #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 509bc8f8c26SIlya Yanok 510bc8f8c26SIlya Yanok #define xstr(s) str(s) 511bc8f8c26SIlya Yanok #define str(s) #s 512bc8f8c26SIlya Yanok 513bc8f8c26SIlya Yanok #define CONFIG_EXTRA_ENV_SETTINGS \ 514bc8f8c26SIlya Yanok "netdev=eth0\0" \ 515bc8f8c26SIlya Yanok "consoledev=ttyS0\0" \ 516bc8f8c26SIlya Yanok "nfsargs=setenv bootargs root=/dev/nfs rw " \ 517bc8f8c26SIlya Yanok "nfsroot=${serverip}:${rootpath}\0" \ 518bc8f8c26SIlya Yanok "ramargs=setenv bootargs root=/dev/ram rw\0" \ 519bc8f8c26SIlya Yanok "addip=setenv bootargs ${bootargs} " \ 520bc8f8c26SIlya Yanok "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 521bc8f8c26SIlya Yanok ":${hostname}:${netdev}:off panic=1\0" \ 522bc8f8c26SIlya Yanok "addtty=setenv bootargs ${bootargs}" \ 523bc8f8c26SIlya Yanok " console=${consoledev},${baudrate}\0" \ 524bc8f8c26SIlya Yanok "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 525bc8f8c26SIlya Yanok "addmisc=setenv bootargs ${bootargs}\0" \ 526bc8f8c26SIlya Yanok "kernel_addr=FC0A0000\0" \ 527bc8f8c26SIlya Yanok "fdt_addr=FC2A0000\0" \ 528bc8f8c26SIlya Yanok "ramdisk_addr=FC2C0000\0" \ 529bc8f8c26SIlya Yanok "u-boot=mpc8308_p1m/u-boot.bin\0" \ 530bc8f8c26SIlya Yanok "kernel_addr_r=1000000\0" \ 531bc8f8c26SIlya Yanok "fdt_addr_r=C00000\0" \ 532bc8f8c26SIlya Yanok "hostname=mpc8308_p1m\0" \ 533bc8f8c26SIlya Yanok "bootfile=mpc8308_p1m/uImage\0" \ 534bc8f8c26SIlya Yanok "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \ 535bc8f8c26SIlya Yanok "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 536bc8f8c26SIlya Yanok "flash_self=run ramargs addip addtty addmtd addmisc;" \ 537bc8f8c26SIlya Yanok "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 538bc8f8c26SIlya Yanok "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 539bc8f8c26SIlya Yanok "bootm ${kernel_addr} - ${fdt_addr}\0" \ 540bc8f8c26SIlya Yanok "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 541bc8f8c26SIlya Yanok "tftp ${fdt_addr_r} ${fdtfile};" \ 542bc8f8c26SIlya Yanok "run nfsargs addip addtty addmtd addmisc;" \ 543bc8f8c26SIlya Yanok "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 544bc8f8c26SIlya Yanok "bootcmd=run flash_self\0" \ 545bc8f8c26SIlya Yanok "load=tftp ${loadaddr} ${u-boot}\0" \ 546bc8f8c26SIlya Yanok "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ 547bc8f8c26SIlya Yanok " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ 548bc8f8c26SIlya Yanok " +${filesize};cp.b ${fileaddr} " \ 549bc8f8c26SIlya Yanok xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 550bc8f8c26SIlya Yanok "upd=run load update\0" \ 551bc8f8c26SIlya Yanok 552bc8f8c26SIlya Yanok #endif /* __CONFIG_H */ 553