1 /* 2 * (C) Copyright 2007-2010 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/xilinx/microblaze-generic/xparameters.h" 13 14 /* MicroBlaze CPU */ 15 #define MICROBLAZE_V5 1 16 17 /* linear and spi flash memory */ 18 #ifdef XILINX_FLASH_START 19 #define FLASH 20 #undef SPIFLASH 21 #undef RAMENV /* hold environment in flash */ 22 #else 23 #ifdef XILINX_SPI_FLASH_BASEADDR 24 #undef FLASH 25 #define SPIFLASH 26 #undef RAMENV /* hold environment in flash */ 27 #else 28 #undef FLASH 29 #undef SPIFLASH 30 #define RAMENV /* hold environment in RAM */ 31 #endif 32 #endif 33 34 /* uart */ 35 # define CONFIG_BAUDRATE 115200 36 /* The following table includes the supported baudrates */ 37 # define CONFIG_SYS_BAUDRATE_TABLE \ 38 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} 39 40 #ifdef XILINX_UARTLITE_BASEADDR 41 # define CONFIG_XILINX_UARTLITE 42 # define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR 43 #elif XILINX_UART16550_BASEADDR 44 # define CONFIG_SYS_NS16550_SERIAL 45 # if defined(__MICROBLAZEEL__) 46 # define CONFIG_SYS_NS16550_REG_SIZE -4 47 # else 48 # define CONFIG_SYS_NS16550_REG_SIZE 4 49 # endif 50 # define CONFIG_CONS_INDEX 1 51 # define CONFIG_SYS_NS16550_COM1 \ 52 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) 53 # define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ 54 #else 55 # error Undefined uart 56 #endif 57 58 /* setting reset address */ 59 /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ 60 61 /* ethernet */ 62 #undef CONFIG_SYS_ENET 63 #if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL) 64 # define CONFIG_XILINX_EMACLITE 1 65 # define CONFIG_SYS_ENET 66 #endif 67 #if defined(XILINX_AXIEMAC_BASEADDR) 68 # define CONFIG_XILINX_AXIEMAC 1 69 # define CONFIG_SYS_ENET 70 #endif 71 72 #undef ET_DEBUG 73 74 /* gpio */ 75 #ifdef XILINX_GPIO_BASEADDR 76 # define CONFIG_XILINX_GPIO 77 # define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR 78 #endif 79 80 /* interrupt controller */ 81 #ifdef XILINX_INTC_BASEADDR 82 # define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR 83 # define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS 84 #endif 85 86 /* timer */ 87 #if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ) 88 # define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR 89 # define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ 90 #endif 91 92 /* watchdog */ 93 #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ) 94 # define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR 95 # define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ 96 # ifndef CONFIG_SPL_BUILD 97 # define CONFIG_HW_WATCHDOG 98 # define CONFIG_XILINX_TB_WATCHDOG 99 # endif 100 #endif 101 102 #if !defined(CONFIG_OF_CONTROL) || \ 103 (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL)) 104 /* ddr sdram - main memory */ 105 # define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START 106 # define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE 107 #endif 108 109 #define CONFIG_SYS_MALLOC_LEN 0xC0000 110 111 /* Stack location before relocation */ 112 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ 113 CONFIG_SYS_MALLOC_F_LEN) 114 115 /* 116 * CFI flash memory layout - Example 117 * CONFIG_SYS_FLASH_BASE = 0x2200_0000; 118 * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB 119 * 120 * SECT_SIZE = 0x20000; 128kB is one sector 121 * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store 122 * 123 * 0x2200_0000 CONFIG_SYS_FLASH_BASE 124 * FREE 256kB 125 * 0x2204_0000 CONFIG_ENV_ADDR 126 * ENV_AREA 128kB 127 * 0x2206_0000 128 * FREE 129 * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE 130 * 131 */ 132 133 #ifdef FLASH 134 # define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START 135 # define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE 136 # define CONFIG_SYS_FLASH_CFI 1 137 # define CONFIG_FLASH_CFI_DRIVER 1 138 /* ?empty sector */ 139 # define CONFIG_SYS_FLASH_EMPTY_INFO 1 140 /* max number of memory banks */ 141 # define CONFIG_SYS_MAX_FLASH_BANKS 1 142 /* max number of sectors on one chip */ 143 # define CONFIG_SYS_MAX_FLASH_SECT 512 144 /* hardware flash protection */ 145 # define CONFIG_SYS_FLASH_PROTECTION 146 /* use buffered writes (20x faster) */ 147 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 148 # ifdef RAMENV 149 # define CONFIG_ENV_IS_NOWHERE 1 150 # define CONFIG_ENV_SIZE 0x1000 151 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) 152 153 # else /* FLASH && !RAMENV */ 154 # define CONFIG_ENV_IS_IN_FLASH 1 155 /* 128K(one sector) for env */ 156 # define CONFIG_ENV_SECT_SIZE 0x20000 157 # define CONFIG_ENV_ADDR \ 158 (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) 159 # define CONFIG_ENV_SIZE 0x20000 160 # endif /* FLASH && !RAMBOOT */ 161 #else /* !FLASH */ 162 163 #ifdef SPIFLASH 164 # define CONFIG_SYS_NO_FLASH 1 165 # define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR 166 # define CONFIG_SPI 1 167 # define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 168 # define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ 169 # define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS 170 171 # ifdef RAMENV 172 # define CONFIG_ENV_IS_NOWHERE 1 173 # define CONFIG_ENV_SIZE 0x1000 174 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) 175 176 # else /* SPIFLASH && !RAMENV */ 177 # define CONFIG_ENV_IS_IN_SPI_FLASH 1 178 # define CONFIG_ENV_SPI_MODE SPI_MODE_3 179 # define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 180 # define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 181 /* 128K(two sectors) for env */ 182 # define CONFIG_ENV_SECT_SIZE 0x10000 183 # define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE) 184 /* Warning: adjust the offset in respect of other flash content and size */ 185 # define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */ 186 # endif /* SPIFLASH && !RAMBOOT */ 187 #else /* !SPIFLASH */ 188 189 /* ENV in RAM */ 190 # define CONFIG_SYS_NO_FLASH 1 191 # define CONFIG_ENV_IS_NOWHERE 1 192 # define CONFIG_ENV_SIZE 0x1000 193 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) 194 #endif /* !SPIFLASH */ 195 #endif /* !FLASH */ 196 197 /* system ace */ 198 #ifdef XILINX_SYSACE_BASEADDR 199 # define CONFIG_SYSTEMACE 200 /* #define DEBUG_SYSTEMACE */ 201 # define SYSTEMACE_CONFIG_FPGA 202 # define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR 203 # define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH 204 # define CONFIG_DOS_PARTITION 205 #endif 206 207 #if defined(XILINX_USE_ICACHE) 208 # define CONFIG_ICACHE 209 #else 210 # undef CONFIG_ICACHE 211 #endif 212 213 #if defined(XILINX_USE_DCACHE) 214 # define CONFIG_DCACHE 215 #else 216 # undef CONFIG_DCACHE 217 #endif 218 219 #ifndef XILINX_DCACHE_BYTE_SIZE 220 #define XILINX_DCACHE_BYTE_SIZE 32768 221 #endif 222 223 /* 224 * BOOTP options 225 */ 226 #define CONFIG_BOOTP_BOOTFILESIZE 227 #define CONFIG_BOOTP_BOOTPATH 228 #define CONFIG_BOOTP_GATEWAY 229 #define CONFIG_BOOTP_HOSTNAME 230 231 /* 232 * Command line configuration. 233 */ 234 #define CONFIG_CMD_ASKENV 235 #define CONFIG_CMD_IRQ 236 #define CONFIG_CMD_MFSL 237 238 #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE) 239 # define CONFIG_CMD_CACHE 240 #else 241 # undef CONFIG_CMD_CACHE 242 #endif 243 244 #ifdef CONFIG_SYS_ENET 245 # define CONFIG_CMD_PING 246 # define CONFIG_CMD_DHCP 247 # define CONFIG_CMD_TFTPPUT 248 #endif 249 250 #if defined(CONFIG_SYSTEMACE) 251 # define CONFIG_CMD_EXT2 252 # define CONFIG_CMD_FAT 253 #endif 254 255 #if defined(FLASH) 256 # define CONFIG_CMD_JFFS2 257 # define CONFIG_CMD_UBI 258 # undef CONFIG_CMD_UBIFS 259 260 # if !defined(RAMENV) 261 # define CONFIG_CMD_SAVES 262 # endif 263 264 #else 265 #if defined(SPIFLASH) 266 # define CONFIG_CMD_SF 267 268 # if !defined(RAMENV) 269 # define CONFIG_CMD_SAVES 270 # endif 271 #else 272 # undef CONFIG_CMD_JFFS2 273 # undef CONFIG_CMD_UBI 274 # undef CONFIG_CMD_UBIFS 275 #endif 276 #endif 277 278 #if defined(CONFIG_CMD_JFFS2) 279 # define CONFIG_MTD_PARTITIONS 280 #endif 281 282 #if defined(CONFIG_CMD_UBIFS) 283 # define CONFIG_CMD_UBI 284 # define CONFIG_LZO 285 #endif 286 287 #if defined(CONFIG_CMD_UBI) 288 # define CONFIG_MTD_PARTITIONS 289 # define CONFIG_RBTREE 290 #endif 291 292 #if defined(CONFIG_MTD_PARTITIONS) 293 /* MTD partitions */ 294 #define CONFIG_CMD_MTDPARTS /* mtdparts command line support */ 295 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 296 #define CONFIG_FLASH_CFI_MTD 297 #define MTDIDS_DEFAULT "nor0=flash-0" 298 299 /* default mtd partition table */ 300 #define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\ 301 "256k(env),3m(kernel),1m(romfs),"\ 302 "1m(cramfs),-(jffs2)" 303 #endif 304 305 /* size of console buffer */ 306 #define CONFIG_SYS_CBSIZE 512 307 /* print buffer size */ 308 #define CONFIG_SYS_PBSIZE \ 309 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 310 /* max number of command args */ 311 #define CONFIG_SYS_MAXARGS 15 312 #define CONFIG_SYS_LONGHELP 313 /* default load address */ 314 #define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START 315 316 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 317 #define CONFIG_BOOTARGS "root=romfs" 318 #define CONFIG_HOSTNAME XILINX_BOARD_NAME 319 #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" 320 #define CONFIG_IPADDR 192.168.0.3 321 #define CONFIG_SERVERIP 192.168.0.5 322 #define CONFIG_GATEWAYIP 192.168.0.1 323 324 /* architecture dependent code */ 325 #define CONFIG_SYS_USR_EXCEP /* user exception */ 326 327 #define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" 328 329 #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ 330 "nor0=flash-0\0"\ 331 "mtdparts=mtdparts=flash-0:"\ 332 "256k(u-boot),256k(env),3m(kernel),"\ 333 "1m(romfs),1m(cramfs),-(jffs2)\0"\ 334 "nc=setenv stdout nc;"\ 335 "setenv stdin nc\0" \ 336 "serial=setenv stdout serial;"\ 337 "setenv stdin serial\0" 338 339 #define CONFIG_CMDLINE_EDITING 340 341 #define CONFIG_NETCONSOLE 342 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 343 344 /* Use the HUSH parser */ 345 #define CONFIG_SYS_HUSH_PARSER 346 347 /* Enable flat device tree support */ 348 #define CONFIG_LMB 1 349 #define CONFIG_FIT 1 350 #define CONFIG_OF_LIBFDT 1 351 352 #if defined(CONFIG_XILINX_AXIEMAC) 353 # define CONFIG_MII 1 354 # define CONFIG_CMD_MII 1 355 # define CONFIG_PHY_GIGE 1 356 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 357 # define CONFIG_PHYLIB 1 358 # define CONFIG_PHY_ATHEROS 1 359 # define CONFIG_PHY_BROADCOM 1 360 # define CONFIG_PHY_DAVICOM 1 361 # define CONFIG_PHY_LXT 1 362 # define CONFIG_PHY_MARVELL 1 363 # define CONFIG_PHY_MICREL 1 364 # define CONFIG_PHY_NATSEMI 1 365 # define CONFIG_PHY_REALTEK 1 366 # define CONFIG_PHY_VITESSE 1 367 #else 368 # undef CONFIG_MII 369 # undef CONFIG_CMD_MII 370 # undef CONFIG_PHYLIB 371 #endif 372 373 /* SPL part */ 374 #define CONFIG_CMD_SPL 375 #define CONFIG_SPL_FRAMEWORK 376 #define CONFIG_SPL_LIBCOMMON_SUPPORT 377 #define CONFIG_SPL_LIBGENERIC_SUPPORT 378 #define CONFIG_SPL_SERIAL_SUPPORT 379 #define CONFIG_SPL_BOARD_INIT 380 381 #define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds" 382 383 #define CONFIG_SPL_RAM_DEVICE 384 #ifdef CONFIG_SYS_FLASH_BASE 385 # define CONFIG_SPL_NOR_SUPPORT 386 # define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE 387 #endif 388 389 /* for booting directly linux */ 390 #define CONFIG_SPL_OS_BOOT 391 392 #define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \ 393 0x60000) 394 #define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ 395 0x40000) 396 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ 397 0x1000000) 398 399 /* SP location before relocation, must use scratch RAM */ 400 /* BRAM start */ 401 #define CONFIG_SYS_INIT_RAM_ADDR 0x0 402 /* BRAM size - will be generated */ 403 #define CONFIG_SYS_INIT_RAM_SIZE 0x100000 404 405 # define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 406 CONFIG_SYS_INIT_RAM_SIZE - \ 407 CONFIG_SYS_MALLOC_F_LEN) 408 409 /* Just for sure that there is a space for stack */ 410 #define CONFIG_SPL_STACK_SIZE 0x100 411 412 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 413 414 #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ 415 CONFIG_SYS_INIT_RAM_ADDR - \ 416 CONFIG_SYS_MALLOC_F_LEN - \ 417 CONFIG_SPL_STACK_SIZE) 418 419 #endif /* __CONFIG_H */ 420