1 /* 2 * (C) Copyright 2007-2010 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/xilinx/microblaze-generic/xparameters.h" 13 14 /* MicroBlaze CPU */ 15 #define MICROBLAZE_V5 1 16 17 /* linear and spi flash memory */ 18 #ifdef XILINX_FLASH_START 19 #define FLASH 20 #undef SPIFLASH 21 #undef RAMENV /* hold environment in flash */ 22 #else 23 #ifdef XILINX_SPI_FLASH_BASEADDR 24 #undef FLASH 25 #define SPIFLASH 26 #undef RAMENV /* hold environment in flash */ 27 #else 28 #undef FLASH 29 #undef SPIFLASH 30 #define RAMENV /* hold environment in RAM */ 31 #endif 32 #endif 33 34 /* uart */ 35 # define CONFIG_BAUDRATE 115200 36 /* The following table includes the supported baudrates */ 37 # define CONFIG_SYS_BAUDRATE_TABLE \ 38 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} 39 40 #if XILINX_UART16550_BASEADDR 41 # define CONFIG_SYS_NS16550_SERIAL 42 # if defined(__MICROBLAZEEL__) 43 # define CONFIG_SYS_NS16550_REG_SIZE -4 44 # else 45 # define CONFIG_SYS_NS16550_REG_SIZE 4 46 # endif 47 # define CONFIG_CONS_INDEX 1 48 # define CONFIG_SYS_NS16550_COM1 \ 49 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) 50 # define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ 51 #endif 52 53 /* setting reset address */ 54 /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ 55 56 /* ethernet */ 57 #undef CONFIG_SYS_ENET 58 #if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL) 59 # define CONFIG_XILINX_EMACLITE 1 60 # define CONFIG_SYS_ENET 61 #endif 62 #if defined(XILINX_AXIEMAC_BASEADDR) 63 # define CONFIG_XILINX_AXIEMAC 1 64 # define CONFIG_SYS_ENET 65 #endif 66 67 #undef ET_DEBUG 68 69 /* gpio */ 70 #ifdef XILINX_GPIO_BASEADDR 71 # define CONFIG_XILINX_GPIO 72 # define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR 73 #endif 74 75 /* interrupt controller */ 76 #ifdef XILINX_INTC_BASEADDR 77 # define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR 78 # define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS 79 #endif 80 81 /* timer */ 82 #if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ) 83 # define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR 84 # define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ 85 #endif 86 87 /* watchdog */ 88 #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ) 89 # define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR 90 # define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ 91 # ifndef CONFIG_SPL_BUILD 92 # define CONFIG_HW_WATCHDOG 93 # define CONFIG_XILINX_TB_WATCHDOG 94 # endif 95 #endif 96 97 #if !defined(CONFIG_OF_CONTROL) || \ 98 (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL)) 99 /* ddr sdram - main memory */ 100 # define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START 101 # define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE 102 #endif 103 104 #define CONFIG_SYS_MALLOC_LEN 0xC0000 105 106 /* Stack location before relocation */ 107 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ 108 CONFIG_SYS_MALLOC_F_LEN) 109 110 /* 111 * CFI flash memory layout - Example 112 * CONFIG_SYS_FLASH_BASE = 0x2200_0000; 113 * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB 114 * 115 * SECT_SIZE = 0x20000; 128kB is one sector 116 * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store 117 * 118 * 0x2200_0000 CONFIG_SYS_FLASH_BASE 119 * FREE 256kB 120 * 0x2204_0000 CONFIG_ENV_ADDR 121 * ENV_AREA 128kB 122 * 0x2206_0000 123 * FREE 124 * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE 125 * 126 */ 127 128 #ifdef FLASH 129 # define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START 130 # define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE 131 # define CONFIG_SYS_FLASH_CFI 1 132 # define CONFIG_FLASH_CFI_DRIVER 1 133 /* ?empty sector */ 134 # define CONFIG_SYS_FLASH_EMPTY_INFO 1 135 /* max number of memory banks */ 136 # define CONFIG_SYS_MAX_FLASH_BANKS 1 137 /* max number of sectors on one chip */ 138 # define CONFIG_SYS_MAX_FLASH_SECT 512 139 /* hardware flash protection */ 140 # define CONFIG_SYS_FLASH_PROTECTION 141 /* use buffered writes (20x faster) */ 142 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 143 # ifdef RAMENV 144 # define CONFIG_ENV_IS_NOWHERE 1 145 # define CONFIG_ENV_SIZE 0x1000 146 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) 147 148 # else /* FLASH && !RAMENV */ 149 # define CONFIG_ENV_IS_IN_FLASH 1 150 /* 128K(one sector) for env */ 151 # define CONFIG_ENV_SECT_SIZE 0x20000 152 # define CONFIG_ENV_ADDR \ 153 (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) 154 # define CONFIG_ENV_SIZE 0x20000 155 # endif /* FLASH && !RAMBOOT */ 156 #else /* !FLASH */ 157 158 #ifdef SPIFLASH 159 # define CONFIG_SYS_NO_FLASH 1 160 # define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR 161 # define CONFIG_SPI 1 162 # define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 163 # define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ 164 # define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS 165 166 # ifdef RAMENV 167 # define CONFIG_ENV_IS_NOWHERE 1 168 # define CONFIG_ENV_SIZE 0x1000 169 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) 170 171 # else /* SPIFLASH && !RAMENV */ 172 # define CONFIG_ENV_IS_IN_SPI_FLASH 1 173 # define CONFIG_ENV_SPI_MODE SPI_MODE_3 174 # define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 175 # define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 176 /* 128K(two sectors) for env */ 177 # define CONFIG_ENV_SECT_SIZE 0x10000 178 # define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE) 179 /* Warning: adjust the offset in respect of other flash content and size */ 180 # define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */ 181 # endif /* SPIFLASH && !RAMBOOT */ 182 #else /* !SPIFLASH */ 183 184 /* ENV in RAM */ 185 # define CONFIG_SYS_NO_FLASH 1 186 # define CONFIG_ENV_IS_NOWHERE 1 187 # define CONFIG_ENV_SIZE 0x1000 188 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) 189 #endif /* !SPIFLASH */ 190 #endif /* !FLASH */ 191 192 /* system ace */ 193 #ifdef XILINX_SYSACE_BASEADDR 194 # define CONFIG_SYSTEMACE 195 /* #define DEBUG_SYSTEMACE */ 196 # define SYSTEMACE_CONFIG_FPGA 197 # define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR 198 # define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH 199 # define CONFIG_DOS_PARTITION 200 #endif 201 202 #if defined(XILINX_USE_ICACHE) 203 # define CONFIG_ICACHE 204 #else 205 # undef CONFIG_ICACHE 206 #endif 207 208 #if defined(XILINX_USE_DCACHE) 209 # define CONFIG_DCACHE 210 #else 211 # undef CONFIG_DCACHE 212 #endif 213 214 #ifndef XILINX_DCACHE_BYTE_SIZE 215 #define XILINX_DCACHE_BYTE_SIZE 32768 216 #endif 217 218 /* 219 * BOOTP options 220 */ 221 #define CONFIG_BOOTP_BOOTFILESIZE 222 #define CONFIG_BOOTP_BOOTPATH 223 #define CONFIG_BOOTP_GATEWAY 224 #define CONFIG_BOOTP_HOSTNAME 225 226 /* 227 * Command line configuration. 228 */ 229 #define CONFIG_CMD_ASKENV 230 #define CONFIG_CMD_IRQ 231 #define CONFIG_CMD_MFSL 232 233 #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE) 234 # define CONFIG_CMD_CACHE 235 #else 236 # undef CONFIG_CMD_CACHE 237 #endif 238 239 #ifdef CONFIG_SYS_ENET 240 # define CONFIG_CMD_PING 241 # define CONFIG_CMD_DHCP 242 # define CONFIG_CMD_TFTPPUT 243 #endif 244 245 #if defined(CONFIG_SYSTEMACE) 246 # define CONFIG_CMD_EXT2 247 # define CONFIG_CMD_FAT 248 #endif 249 250 #if defined(FLASH) 251 # define CONFIG_CMD_JFFS2 252 # define CONFIG_CMD_UBI 253 # undef CONFIG_CMD_UBIFS 254 255 # if !defined(RAMENV) 256 # define CONFIG_CMD_SAVES 257 # endif 258 259 #else 260 #if defined(SPIFLASH) 261 # define CONFIG_CMD_SF 262 263 # if !defined(RAMENV) 264 # define CONFIG_CMD_SAVES 265 # endif 266 #else 267 # undef CONFIG_CMD_JFFS2 268 # undef CONFIG_CMD_UBI 269 # undef CONFIG_CMD_UBIFS 270 #endif 271 #endif 272 273 #if defined(CONFIG_CMD_JFFS2) 274 # define CONFIG_MTD_PARTITIONS 275 #endif 276 277 #if defined(CONFIG_CMD_UBIFS) 278 # define CONFIG_CMD_UBI 279 # define CONFIG_LZO 280 #endif 281 282 #if defined(CONFIG_CMD_UBI) 283 # define CONFIG_MTD_PARTITIONS 284 # define CONFIG_RBTREE 285 #endif 286 287 #if defined(CONFIG_MTD_PARTITIONS) 288 /* MTD partitions */ 289 #define CONFIG_CMD_MTDPARTS /* mtdparts command line support */ 290 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 291 #define CONFIG_FLASH_CFI_MTD 292 #define MTDIDS_DEFAULT "nor0=flash-0" 293 294 /* default mtd partition table */ 295 #define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\ 296 "256k(env),3m(kernel),1m(romfs),"\ 297 "1m(cramfs),-(jffs2)" 298 #endif 299 300 /* size of console buffer */ 301 #define CONFIG_SYS_CBSIZE 512 302 /* print buffer size */ 303 #define CONFIG_SYS_PBSIZE \ 304 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 305 /* max number of command args */ 306 #define CONFIG_SYS_MAXARGS 15 307 #define CONFIG_SYS_LONGHELP 308 /* default load address */ 309 #define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START 310 311 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 312 #define CONFIG_BOOTARGS "root=romfs" 313 #define CONFIG_HOSTNAME XILINX_BOARD_NAME 314 #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" 315 #define CONFIG_IPADDR 192.168.0.3 316 #define CONFIG_SERVERIP 192.168.0.5 317 #define CONFIG_GATEWAYIP 192.168.0.1 318 319 /* architecture dependent code */ 320 #define CONFIG_SYS_USR_EXCEP /* user exception */ 321 322 #define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" 323 324 #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ 325 "nor0=flash-0\0"\ 326 "mtdparts=mtdparts=flash-0:"\ 327 "256k(u-boot),256k(env),3m(kernel),"\ 328 "1m(romfs),1m(cramfs),-(jffs2)\0"\ 329 "nc=setenv stdout nc;"\ 330 "setenv stdin nc\0" \ 331 "serial=setenv stdout serial;"\ 332 "setenv stdin serial\0" 333 334 #define CONFIG_CMDLINE_EDITING 335 336 #define CONFIG_NETCONSOLE 337 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 338 339 /* Use the HUSH parser */ 340 #define CONFIG_SYS_HUSH_PARSER 341 342 /* Enable flat device tree support */ 343 #define CONFIG_LMB 1 344 #define CONFIG_FIT 1 345 #define CONFIG_OF_LIBFDT 1 346 347 #if defined(CONFIG_XILINX_AXIEMAC) 348 # define CONFIG_MII 1 349 # define CONFIG_CMD_MII 1 350 # define CONFIG_PHY_GIGE 1 351 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 352 # define CONFIG_PHYLIB 1 353 # define CONFIG_PHY_ATHEROS 1 354 # define CONFIG_PHY_BROADCOM 1 355 # define CONFIG_PHY_DAVICOM 1 356 # define CONFIG_PHY_LXT 1 357 # define CONFIG_PHY_MARVELL 1 358 # define CONFIG_PHY_MICREL 1 359 # define CONFIG_PHY_NATSEMI 1 360 # define CONFIG_PHY_REALTEK 1 361 # define CONFIG_PHY_VITESSE 1 362 #else 363 # undef CONFIG_MII 364 # undef CONFIG_CMD_MII 365 # undef CONFIG_PHYLIB 366 #endif 367 368 /* SPL part */ 369 #define CONFIG_CMD_SPL 370 #define CONFIG_SPL_FRAMEWORK 371 #define CONFIG_SPL_LIBCOMMON_SUPPORT 372 #define CONFIG_SPL_LIBGENERIC_SUPPORT 373 #define CONFIG_SPL_SERIAL_SUPPORT 374 #define CONFIG_SPL_BOARD_INIT 375 376 #define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds" 377 378 #define CONFIG_SPL_RAM_DEVICE 379 #ifdef CONFIG_SYS_FLASH_BASE 380 # define CONFIG_SPL_NOR_SUPPORT 381 # define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE 382 #endif 383 384 /* for booting directly linux */ 385 #define CONFIG_SPL_OS_BOOT 386 387 #define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \ 388 0x60000) 389 #define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ 390 0x40000) 391 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ 392 0x1000000) 393 394 /* SP location before relocation, must use scratch RAM */ 395 /* BRAM start */ 396 #define CONFIG_SYS_INIT_RAM_ADDR 0x0 397 /* BRAM size - will be generated */ 398 #define CONFIG_SYS_INIT_RAM_SIZE 0x100000 399 400 # define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 401 CONFIG_SYS_INIT_RAM_SIZE - \ 402 CONFIG_SYS_MALLOC_F_LEN) 403 404 /* Just for sure that there is a space for stack */ 405 #define CONFIG_SPL_STACK_SIZE 0x100 406 407 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 408 409 #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ 410 CONFIG_SYS_INIT_RAM_ADDR - \ 411 CONFIG_SYS_MALLOC_F_LEN - \ 412 CONFIG_SPL_STACK_SIZE) 413 414 #endif /* __CONFIG_H */ 415