1 /* 2 * (C) Copyright 2007-2008 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef __CONFIG_H 26 #define __CONFIG_H 27 28 #include "../board/xilinx/microblaze-generic/xparameters.h" 29 30 #define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */ 31 #define MICROBLAZE_V5 1 32 33 /* uart */ 34 #ifdef XILINX_UARTLITE_BASEADDR 35 #define CONFIG_XILINX_UARTLITE 36 #define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR 37 #define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE 38 #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } 39 #elif XILINX_UART16550_BASEADDR 40 #define CONFIG_SYS_NS16550 1 41 #define CONFIG_SYS_NS16550_SERIAL 42 #define CONFIG_SYS_NS16550_REG_SIZE -4 43 #define CONFIG_CONS_INDEX 1 44 #define CONFIG_SYS_NS16550_COM1 (XILINX_UART16550_BASEADDR + 0x1000 + 0x3) 45 #define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ 46 #define CONFIG_BAUDRATE 115200 47 48 /* The following table includes the supported baudrates */ 49 #define CONFIG_SYS_BAUDRATE_TABLE \ 50 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} 51 #else 52 #error Undefined uart 53 #endif 54 55 /* setting reset address */ 56 /*#define CONFIG_SYS_RESET_ADDRESS TEXT_BASE*/ 57 58 /* ethernet */ 59 #ifdef XILINX_EMAC_BASEADDR 60 #define CONFIG_XILINX_EMAC 1 61 #define CONFIG_SYS_ENET 62 #else 63 #ifdef XILINX_EMACLITE_BASEADDR 64 #define CONFIG_XILINX_EMACLITE 1 65 #define CONFIG_SYS_ENET 66 #endif 67 #endif 68 #undef ET_DEBUG 69 70 /* gpio */ 71 #ifdef XILINX_GPIO_BASEADDR 72 #define CONFIG_SYS_GPIO_0 1 73 #define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR 74 #endif 75 76 /* interrupt controller */ 77 #ifdef XILINX_INTC_BASEADDR 78 #define CONFIG_SYS_INTC_0 1 79 #define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR 80 #define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS 81 #endif 82 83 /* timer */ 84 #ifdef XILINX_TIMER_BASEADDR 85 #if (XILINX_TIMER_IRQ != -1) 86 #define CONFIG_SYS_TIMER_0 1 87 #define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR 88 #define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ 89 #define FREQUENCE XILINX_CLOCK_FREQ 90 #define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) 91 #endif 92 #else 93 #ifdef XILINX_CLOCK_FREQ 94 #define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ 95 #else 96 #error BAD CLOCK FREQ 97 #endif 98 #endif 99 /* FSL */ 100 /* #define CONFIG_SYS_FSL_2 */ 101 /* #define FSL_INTR_2 1 */ 102 103 /* 104 * memory layout - Example 105 * TEXT_BASE = 0x1200_0000; 106 * CONFIG_SYS_SRAM_BASE = 0x1000_0000; 107 * CONFIG_SYS_SRAM_SIZE = 0x0400_0000; 108 * 109 * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000 110 * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000 111 * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 112 * 113 * 0x1000_0000 CONFIG_SYS_SDRAM_BASE 114 * FREE 115 * 0x1200_0000 TEXT_BASE 116 * U-BOOT code 117 * 0x1202_0000 118 * FREE 119 * 120 * STACK 121 * 0x13F7_F000 CONFIG_SYS_MALLOC_BASE 122 * MALLOC_AREA 256kB Alloc 123 * 0x11FB_F000 CONFIG_SYS_MONITOR_BASE 124 * MONITOR_CODE 256kB Env 125 * 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET 126 * GLOBAL_DATA 4kB bd, gd 127 * 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE 128 */ 129 130 /* ddr sdram - main memory */ 131 #define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START 132 #define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE 133 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 134 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) 135 136 /* global pointer */ 137 #define CONFIG_SYS_GBL_DATA_SIZE 0x1000 /* size of global data */ 138 /* start of global data */ 139 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) 140 141 /* monitor code */ 142 #define SIZE 0x40000 143 #define CONFIG_SYS_MONITOR_LEN SIZE 144 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN) 145 #define CONFIG_SYS_MONITOR_END (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 146 #define CONFIG_SYS_MALLOC_LEN SIZE 147 #define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) 148 149 /* stack */ 150 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MONITOR_BASE 151 152 /*#define RAMENV */ 153 #define FLASH 154 155 #ifdef FLASH 156 #define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START 157 #define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE 158 #define CONFIG_SYS_FLASH_CFI 1 159 #define CONFIG_FLASH_CFI_DRIVER 1 160 #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* ?empty sector */ 161 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 162 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ 163 #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */ 164 165 #ifdef RAMENV 166 #define CONFIG_ENV_IS_NOWHERE 1 167 #define CONFIG_ENV_SIZE 0x1000 168 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) 169 170 #else /* !RAMENV */ 171 #define CONFIG_ENV_IS_IN_FLASH 1 172 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 173 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) 174 #define CONFIG_ENV_SIZE 0x40000 175 #endif /* !RAMBOOT */ 176 #else /* !FLASH */ 177 /* ENV in RAM */ 178 #define CONFIG_SYS_NO_FLASH 1 179 #define CONFIG_ENV_IS_NOWHERE 1 180 #define CONFIG_ENV_SIZE 0x1000 181 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) 182 #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */ 183 #endif /* !FLASH */ 184 185 /* system ace */ 186 #ifdef XILINX_SYSACE_BASEADDR 187 #define CONFIG_SYSTEMACE 188 /* #define DEBUG_SYSTEMACE */ 189 #define SYSTEMACE_CONFIG_FPGA 190 #define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR 191 #define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH 192 #define CONFIG_DOS_PARTITION 193 #endif 194 195 /* 196 * BOOTP options 197 */ 198 #define CONFIG_BOOTP_BOOTFILESIZE 199 #define CONFIG_BOOTP_BOOTPATH 200 #define CONFIG_BOOTP_GATEWAY 201 #define CONFIG_BOOTP_HOSTNAME 202 203 /* 204 * Command line configuration. 205 */ 206 #include <config_cmd_default.h> 207 208 #define CONFIG_CMD_ASKENV 209 #define CONFIG_CMD_CACHE 210 #define CONFIG_CMD_IRQ 211 #define CONFIG_CMD_MFSL 212 213 #ifndef CONFIG_SYS_ENET 214 #undef CONFIG_CMD_NET 215 #else 216 #define CONFIG_CMD_PING 217 #endif 218 219 #if defined(CONFIG_SYSTEMACE) 220 #define CONFIG_CMD_EXT2 221 #define CONFIG_CMD_FAT 222 #endif 223 224 #if defined(FLASH) 225 #define CONFIG_CMD_ECHO 226 #define CONFIG_CMD_FLASH 227 #define CONFIG_CMD_IMLS 228 #define CONFIG_CMD_JFFS2 229 230 #if !defined(RAMENV) 231 #define CONFIG_CMD_ENV 232 #define CONFIG_CMD_SAVES 233 #endif 234 #else 235 #undef CONFIG_CMD_FLASH 236 #endif 237 238 #if defined(CONFIG_CMD_JFFS2) 239 /* JFFS2 partitions */ 240 #define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */ 241 #define MTDIDS_DEFAULT "nor0=ml401-0" 242 243 /* default mtd partition table */ 244 #define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\ 245 "256k(env),3m(kernel),1m(romfs),"\ 246 "1m(cramfs),-(jffs2)" 247 #endif 248 249 /* Miscellaneous configurable options */ 250 #define CONFIG_SYS_PROMPT "U-Boot-mONStR> " 251 #define CONFIG_SYS_CBSIZE 512 /* size of console buffer */ 252 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ 253 #define CONFIG_SYS_MAXARGS 15 /* max number of command args */ 254 #define CONFIG_SYS_LONGHELP 255 #define CONFIG_SYS_LOAD_ADDR 0x12000000 /* default load address */ 256 257 #define CONFIG_BOOTDELAY 30 258 #define CONFIG_BOOTARGS "root=romfs" 259 #define CONFIG_HOSTNAME "ml401" 260 #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" 261 #define CONFIG_IPADDR 192.168.0.3 262 #define CONFIG_SERVERIP 192.168.0.5 263 #define CONFIG_GATEWAYIP 192.168.0.1 264 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 265 266 /* architecture dependent code */ 267 #define CONFIG_SYS_USR_EXCEP /* user exception */ 268 #define CONFIG_SYS_HZ 1000 269 270 #define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo" 271 272 #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\ 273 "nor0=ml401-0\0"\ 274 "mtdparts=mtdparts=ml401-0:"\ 275 "256k(u-boot),256k(env),3m(kernel),"\ 276 "1m(romfs),1m(cramfs),-(jffs2)\0" 277 278 #define CONFIG_CMDLINE_EDITING 279 280 #endif /* __CONFIG_H */ 281