xref: /openbmc/u-boot/include/configs/microblaze-generic.h (revision 24b852a7a2b8eca71789100983bdb5104cc00696)
1 /*
2  * (C) Copyright 2007-2010 Michal Simek
3  *
4  * Michal SIMEK <monstr@monstr.eu>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 #include "../board/xilinx/microblaze-generic/xparameters.h"
13 
14 /* MicroBlaze CPU */
15 #define	MICROBLAZE_V5		1
16 
17 /* linear and spi flash memory */
18 #ifdef XILINX_FLASH_START
19 #define	FLASH
20 #undef	SPIFLASH
21 #undef	RAMENV	/* hold environment in flash */
22 #else
23 #ifdef XILINX_SPI_FLASH_BASEADDR
24 #undef	FLASH
25 #define	SPIFLASH
26 #undef	RAMENV	/* hold environment in flash */
27 #else
28 #undef	FLASH
29 #undef	SPIFLASH
30 #define	RAMENV	/* hold environment in RAM */
31 #endif
32 #endif
33 
34 /* uart */
35 #ifdef XILINX_UARTLITE_BASEADDR
36 # define CONFIG_XILINX_UARTLITE
37 # define CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
38 # define CONFIG_BAUDRATE	XILINX_UARTLITE_BAUDRATE
39 # define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
40 # define CONSOLE_ARG	"console=console=ttyUL0,115200\0"
41 #elif XILINX_UART16550_BASEADDR
42 # define CONFIG_SYS_NS16550		1
43 # define CONFIG_SYS_NS16550_SERIAL
44 # if defined(__MICROBLAZEEL__)
45 #  define CONFIG_SYS_NS16550_REG_SIZE	-4
46 # else
47 #  define CONFIG_SYS_NS16550_REG_SIZE	4
48 # endif
49 # define CONFIG_CONS_INDEX		1
50 # define CONFIG_SYS_NS16550_COM1 \
51 		((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
52 # define CONFIG_SYS_NS16550_CLK	XILINX_UART16550_CLOCK_HZ
53 # define CONFIG_BAUDRATE	115200
54 
55 /* The following table includes the supported baudrates */
56 # define CONFIG_SYS_BAUDRATE_TABLE \
57 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
58 # define CONSOLE_ARG	"console=console=ttyS0,115200\0"
59 #else
60 # error Undefined uart
61 #endif
62 
63 /* setting reset address */
64 /*#define	CONFIG_SYS_RESET_ADDRESS	CONFIG_SYS_TEXT_BASE*/
65 
66 /* ethernet */
67 #undef CONFIG_SYS_ENET
68 #if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL)
69 # define CONFIG_XILINX_EMACLITE	1
70 # define CONFIG_SYS_ENET
71 #endif
72 #if defined(XILINX_LLTEMAC_BASEADDR)
73 # define CONFIG_XILINX_LL_TEMAC	1
74 # define CONFIG_SYS_ENET
75 #endif
76 #if defined(XILINX_AXIEMAC_BASEADDR)
77 # define CONFIG_XILINX_AXIEMAC	1
78 # define CONFIG_SYS_ENET
79 #endif
80 
81 #undef ET_DEBUG
82 
83 /* gpio */
84 #ifdef XILINX_GPIO_BASEADDR
85 # define CONFIG_XILINX_GPIO
86 # define CONFIG_SYS_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
87 #endif
88 
89 /* interrupt controller */
90 #ifdef XILINX_INTC_BASEADDR
91 # define CONFIG_SYS_INTC_0_ADDR		XILINX_INTC_BASEADDR
92 # define CONFIG_SYS_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS
93 #endif
94 
95 /* timer */
96 #if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
97 #  define CONFIG_SYS_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
98 #  define CONFIG_SYS_TIMER_0_IRQ	XILINX_TIMER_IRQ
99 #endif
100 
101 /* watchdog */
102 #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
103 # define CONFIG_WATCHDOG_BASEADDR	XILINX_WATCHDOG_BASEADDR
104 # define CONFIG_WATCHDOG_IRQ		XILINX_WATCHDOG_IRQ
105 # define CONFIG_HW_WATCHDOG
106 # define CONFIG_XILINX_TB_WATCHDOG
107 #endif
108 
109 #if !defined(CONFIG_OF_CONTROL) || \
110 	(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL))
111 /* ddr sdram - main memory */
112 # define CONFIG_SYS_SDRAM_BASE	XILINX_RAM_START
113 # define CONFIG_SYS_SDRAM_SIZE	XILINX_RAM_SIZE
114 #endif
115 
116 #define CONFIG_SYS_MALLOC_LEN	0xC0000
117 #ifndef CONFIG_SPL_BUILD
118 # define CONFIG_SYS_MALLOC_F_LEN	1024
119 #else
120 # define CONFIG_SYS_MALLOC_SIMPLE
121 # define CONFIG_SYS_MALLOC_F_LEN	0x150
122 #endif
123 
124 /* Stack location before relocation */
125 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_TEXT_BASE
126 
127 /*
128  * CFI flash memory layout - Example
129  * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
130  * CONFIG_SYS_FLASH_SIZE = 0x0080_0000;	  8MB
131  *
132  * SECT_SIZE = 0x20000;			128kB is one sector
133  * CONFIG_ENV_SIZE = SECT_SIZE;		128kB environment store
134  *
135  * 0x2200_0000	CONFIG_SYS_FLASH_BASE
136  *					FREE		256kB
137  * 0x2204_0000	CONFIG_ENV_ADDR
138  *					ENV_AREA	128kB
139  * 0x2206_0000
140  *					FREE
141  * 0x2280_0000	CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
142  *
143  */
144 
145 #ifdef FLASH
146 # define CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
147 # define CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
148 # define CONFIG_SYS_FLASH_CFI		1
149 # define CONFIG_FLASH_CFI_DRIVER	1
150 /* ?empty sector */
151 # define CONFIG_SYS_FLASH_EMPTY_INFO	1
152 /* max number of memory banks */
153 # define CONFIG_SYS_MAX_FLASH_BANKS	1
154 /* max number of sectors on one chip */
155 # define CONFIG_SYS_MAX_FLASH_SECT	512
156 /* hardware flash protection */
157 # define CONFIG_SYS_FLASH_PROTECTION
158 /* use buffered writes (20x faster) */
159 # define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
160 # ifdef	RAMENV
161 #  define CONFIG_ENV_IS_NOWHERE	1
162 #  define CONFIG_ENV_SIZE	0x1000
163 #  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
164 
165 # else	/* FLASH && !RAMENV */
166 #  define CONFIG_ENV_IS_IN_FLASH	1
167 /* 128K(one sector) for env */
168 #  define CONFIG_ENV_SECT_SIZE	0x20000
169 #  define CONFIG_ENV_ADDR \
170 			(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
171 #  define CONFIG_ENV_SIZE	0x20000
172 # endif /* FLASH && !RAMBOOT */
173 #else /* !FLASH */
174 
175 #ifdef SPIFLASH
176 # define CONFIG_SYS_NO_FLASH		1
177 # define CONFIG_SYS_SPI_BASE		XILINX_SPI_FLASH_BASEADDR
178 # define CONFIG_XILINX_SPI		1
179 # define CONFIG_SPI			1
180 # define CONFIG_SPI_FLASH_STMICRO	1
181 # define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
182 # define CONFIG_SF_DEFAULT_SPEED	XILINX_SPI_FLASH_MAX_FREQ
183 # define CONFIG_SF_DEFAULT_CS		XILINX_SPI_FLASH_CS
184 
185 # ifdef	RAMENV
186 #  define CONFIG_ENV_IS_NOWHERE	1
187 #  define CONFIG_ENV_SIZE	0x1000
188 #  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
189 
190 # else	/* SPIFLASH && !RAMENV */
191 #  define CONFIG_ENV_IS_IN_SPI_FLASH	1
192 #  define CONFIG_ENV_SPI_MODE		SPI_MODE_3
193 #  define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
194 #  define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
195 /* 128K(two sectors) for env */
196 #  define CONFIG_ENV_SECT_SIZE	0x10000
197 #  define CONFIG_ENV_SIZE	(2 * CONFIG_ENV_SECT_SIZE)
198 /* Warning: adjust the offset in respect of other flash content and size */
199 #  define CONFIG_ENV_OFFSET	(128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
200 # endif /* SPIFLASH && !RAMBOOT */
201 #else /* !SPIFLASH */
202 
203 /* ENV in RAM */
204 # define CONFIG_SYS_NO_FLASH	1
205 # define CONFIG_ENV_IS_NOWHERE	1
206 # define CONFIG_ENV_SIZE	0x1000
207 # define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
208 #endif /* !SPIFLASH */
209 #endif /* !FLASH */
210 
211 /* system ace */
212 #ifdef XILINX_SYSACE_BASEADDR
213 # define CONFIG_SYSTEMACE
214 /* #define DEBUG_SYSTEMACE */
215 # define SYSTEMACE_CONFIG_FPGA
216 # define CONFIG_SYS_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
217 # define CONFIG_SYS_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
218 # define CONFIG_DOS_PARTITION
219 #endif
220 
221 #if defined(XILINX_USE_ICACHE)
222 # define CONFIG_ICACHE
223 #else
224 # undef CONFIG_ICACHE
225 #endif
226 
227 #if defined(XILINX_USE_DCACHE)
228 # define CONFIG_DCACHE
229 #else
230 # undef CONFIG_DCACHE
231 #endif
232 
233 #ifndef XILINX_DCACHE_BYTE_SIZE
234 #define XILINX_DCACHE_BYTE_SIZE	32768
235 #endif
236 
237 /*
238  * BOOTP options
239  */
240 #define CONFIG_BOOTP_BOOTFILESIZE
241 #define CONFIG_BOOTP_BOOTPATH
242 #define CONFIG_BOOTP_GATEWAY
243 #define CONFIG_BOOTP_HOSTNAME
244 
245 /*
246  * Command line configuration.
247  */
248 #define CONFIG_CMD_ASKENV
249 #define CONFIG_CMD_IRQ
250 #define CONFIG_CMD_MFSL
251 
252 #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
253 # define CONFIG_CMD_CACHE
254 #else
255 # undef CONFIG_CMD_CACHE
256 #endif
257 
258 #ifdef CONFIG_SYS_ENET
259 # define CONFIG_CMD_PING
260 # define CONFIG_CMD_DHCP
261 # define CONFIG_CMD_TFTPPUT
262 #endif
263 
264 #if defined(CONFIG_SYSTEMACE)
265 # define CONFIG_CMD_EXT2
266 # define CONFIG_CMD_FAT
267 #endif
268 
269 #if defined(FLASH)
270 # define CONFIG_CMD_JFFS2
271 # define CONFIG_CMD_UBI
272 # undef CONFIG_CMD_UBIFS
273 
274 # if !defined(RAMENV)
275 #  define CONFIG_CMD_SAVES
276 # endif
277 
278 #else
279 #if defined(SPIFLASH)
280 # define CONFIG_CMD_SF
281 
282 # if !defined(RAMENV)
283 #  define CONFIG_CMD_SAVES
284 # endif
285 #else
286 # undef CONFIG_CMD_JFFS2
287 # undef CONFIG_CMD_UBI
288 # undef CONFIG_CMD_UBIFS
289 #endif
290 #endif
291 
292 #if defined(CONFIG_CMD_JFFS2)
293 # define CONFIG_MTD_PARTITIONS
294 #endif
295 
296 #if defined(CONFIG_CMD_UBIFS)
297 # define CONFIG_CMD_UBI
298 # define CONFIG_LZO
299 #endif
300 
301 #if defined(CONFIG_CMD_UBI)
302 # define CONFIG_MTD_PARTITIONS
303 # define CONFIG_RBTREE
304 #endif
305 
306 #if defined(CONFIG_MTD_PARTITIONS)
307 /* MTD partitions */
308 #define CONFIG_CMD_MTDPARTS	/* mtdparts command line support */
309 #define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
310 #define CONFIG_FLASH_CFI_MTD
311 #define MTDIDS_DEFAULT		"nor0=flash-0"
312 
313 /* default mtd partition table */
314 #define MTDPARTS_DEFAULT	"mtdparts=flash-0:256k(u-boot),"\
315 				"256k(env),3m(kernel),1m(romfs),"\
316 				"1m(cramfs),-(jffs2)"
317 #endif
318 
319 /* size of console buffer */
320 #define	CONFIG_SYS_CBSIZE	512
321  /* print buffer size */
322 #define	CONFIG_SYS_PBSIZE \
323 		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
324 /* max number of command args */
325 #define	CONFIG_SYS_MAXARGS	15
326 #define	CONFIG_SYS_LONGHELP
327 /* default load address */
328 #define	CONFIG_SYS_LOAD_ADDR	XILINX_RAM_START
329 
330 #define	CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
331 #define	CONFIG_BOOTARGS		"root=romfs"
332 #define	CONFIG_HOSTNAME		XILINX_BOARD_NAME
333 #define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
334 #define	CONFIG_IPADDR		192.168.0.3
335 #define	CONFIG_SERVERIP		192.168.0.5
336 #define	CONFIG_GATEWAYIP	192.168.0.1
337 
338 /* architecture dependent code */
339 #define	CONFIG_SYS_USR_EXCEP	/* user exception */
340 
341 #define	CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot;echo"
342 
343 #define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" \
344 					"nor0=flash-0\0"\
345 					"mtdparts=mtdparts=flash-0:"\
346 					"256k(u-boot),256k(env),3m(kernel),"\
347 					"1m(romfs),1m(cramfs),-(jffs2)\0"\
348 					"nc=setenv stdout nc;"\
349 					"setenv stdin nc\0" \
350 					"serial=setenv stdout serial;"\
351 					"setenv stdin serial\0"
352 
353 #define CONFIG_CMDLINE_EDITING
354 
355 #define CONFIG_NETCONSOLE
356 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
357 
358 /* Use the HUSH parser */
359 #define CONFIG_SYS_HUSH_PARSER
360 
361 /* Enable flat device tree support */
362 #define CONFIG_LMB		1
363 #define CONFIG_FIT		1
364 #define CONFIG_OF_LIBFDT	1
365 
366 #if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC)
367 # define CONFIG_MII		1
368 # define CONFIG_CMD_MII		1
369 # define CONFIG_PHY_GIGE	1
370 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
371 # define CONFIG_PHYLIB		1
372 # define CONFIG_PHY_ATHEROS	1
373 # define CONFIG_PHY_BROADCOM	1
374 # define CONFIG_PHY_DAVICOM	1
375 # define CONFIG_PHY_LXT		1
376 # define CONFIG_PHY_MARVELL	1
377 # define CONFIG_PHY_MICREL	1
378 # define CONFIG_PHY_NATSEMI	1
379 # define CONFIG_PHY_REALTEK	1
380 # define CONFIG_PHY_VITESSE	1
381 #else
382 # undef CONFIG_MII
383 # undef CONFIG_CMD_MII
384 # undef CONFIG_PHYLIB
385 #endif
386 
387 /* SPL part */
388 #define CONFIG_CMD_SPL
389 #define CONFIG_SPL_FRAMEWORK
390 #define CONFIG_SPL_LIBCOMMON_SUPPORT
391 #define CONFIG_SPL_LIBGENERIC_SUPPORT
392 #define CONFIG_SPL_SERIAL_SUPPORT
393 #define CONFIG_SPL_BOARD_INIT
394 
395 #define CONFIG_SPL_LDSCRIPT	"arch/microblaze/cpu/u-boot-spl.lds"
396 
397 #define CONFIG_SPL_RAM_DEVICE
398 #ifdef CONFIG_SYS_FLASH_BASE
399 # define CONFIG_SPL_NOR_SUPPORT
400 # define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_FLASH_BASE
401 #endif
402 
403 /* for booting directly linux */
404 #define CONFIG_SPL_OS_BOOT
405 
406 #define CONFIG_SYS_OS_BASE		(CONFIG_SYS_FLASH_BASE + \
407 					 0x60000)
408 #define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
409 					 0x40000)
410 #define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_TEXT_BASE + \
411 					 0x1000000)
412 
413 /* SP location before relocation, must use scratch RAM */
414 /* BRAM start */
415 #define CONFIG_SYS_INIT_RAM_ADDR	0x0
416 /* BRAM size - will be generated */
417 #define CONFIG_SYS_INIT_RAM_SIZE	0x100000
418 
419 # define CONFIG_SPL_STACK_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
420 					 CONFIG_SYS_INIT_RAM_SIZE - \
421 					 CONFIG_SYS_MALLOC_F_LEN)
422 
423 /* Just for sure that there is a space for stack */
424 #define CONFIG_SPL_STACK_SIZE		0x100
425 
426 #define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
427 
428 #define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_INIT_RAM_SIZE - \
429 					 CONFIG_SYS_INIT_RAM_ADDR - \
430 					 CONFIG_SYS_MALLOC_F_LEN - \
431 					 CONFIG_SPL_STACK_SIZE)
432 
433 #endif	/* __CONFIG_H */
434