1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2007-2008 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * 7 * (C) Copyright 2009-2015 8 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 9 * esd electronic system design gmbh <www.esd.eu> 10 * 11 * Configuation settings for the esd MEESC board. 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 /* 18 * SoC must be defined first, before hardware.h is included. 19 * In this case SoC is defined in boards.cfg. 20 */ 21 #include <asm/hardware.h> 22 23 /* 24 * Warning: changing CONFIG_SYS_TEXT_BASE requires 25 * adapting the initial boot program. 26 * Since the linker has to swallow that define, we must use a pure 27 * hex number here! 28 */ 29 30 /* ARM asynchronous clock */ 31 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ 32 #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ 33 34 /* Misc CPU related */ 35 #define CONFIG_SKIP_LOWLEVEL_INIT 36 #define CONFIG_ARCH_CPU_INIT 37 #define CONFIG_SETUP_MEMORY_TAGS 38 #define CONFIG_INITRD_TAG 39 #define CONFIG_SERIAL_TAG 40 #define CONFIG_REVISION_TAG 41 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 42 #define CONFIG_MISC_INIT_R /* Call misc_init_r */ 43 44 #define CONFIG_PREBOOT /* enable preboot variable */ 45 46 /* 47 * Hardware drivers 48 */ 49 50 /* 51 * BOOTP options 52 */ 53 #define CONFIG_BOOTP_BOOTFILESIZE 54 55 /* 56 * SDRAM: 1 bank, min 32, max 128 MB 57 * Initialized before u-boot gets started. 58 */ 59 #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ 60 #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */ 61 62 #define CONFIG_NR_DRAM_BANKS 1 63 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 64 #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE 65 66 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) 67 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000) 68 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000) 69 70 /* 71 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, 72 * leaving the correct space for initial global data structure above 73 * that address while providing maximum stack area below. 74 */ 75 #define CONFIG_SYS_INIT_SP_ADDR \ 76 (ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 77 78 /* NAND flash */ 79 #ifdef CONFIG_CMD_NAND 80 # define CONFIG_NAND_ATMEL 81 # define CONFIG_SYS_MAX_NAND_DEVICE 1 82 # define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ 83 # define CONFIG_SYS_NAND_DBW_8 84 # define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 85 # define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 86 # define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) 87 # define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) 88 #endif 89 90 /* Ethernet */ 91 #define CONFIG_MACB 92 #define CONFIG_RMII 93 #define CONFIG_NET_RETRY_COUNT 20 94 #undef CONFIG_RESET_PHY_R 95 96 /* hw-controller addresses */ 97 #define CONFIG_ET1100_BASE 0x70000000 98 99 #ifdef CONFIG_SYS_USE_DATAFLASH 100 101 /* bootstrap + u-boot + env in dataflash on CS0 */ 102 #define CONFIG_ENV_OFFSET 0x4200 103 #define CONFIG_ENV_SIZE 0x4200 104 #define CONFIG_ENV_SECT_SIZE 0x210 105 #define CONFIG_ENV_SPI_MAX_HZ 15000000 106 107 #elif CONFIG_SYS_USE_NANDFLASH 108 109 /* bootstrap + u-boot + env + linux in nandflash */ 110 # define CONFIG_ENV_OFFSET 0xC0000 111 # define CONFIG_ENV_SIZE 0x20000 112 113 #endif 114 115 #define CONFIG_SYS_CBSIZE 512 116 117 /* 118 * Size of malloc() pool 119 */ 120 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ 121 128*1024, 0x1000) 122 123 #endif 124