1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * (C) Copyright 2009-2015 7 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 8 * esd electronic system design gmbh <www.esd.eu> 9 * 10 * Configuation settings for the esd MEESC board. 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 /* 19 * SoC must be defined first, before hardware.h is included. 20 * In this case SoC is defined in boards.cfg. 21 */ 22 #include <asm/hardware.h> 23 24 /* 25 * Warning: changing CONFIG_SYS_TEXT_BASE requires 26 * adapting the initial boot program. 27 * Since the linker has to swallow that define, we must use a pure 28 * hex number here! 29 */ 30 31 /* ARM asynchronous clock */ 32 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ 33 #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ 34 35 /* Misc CPU related */ 36 #define CONFIG_SKIP_LOWLEVEL_INIT 37 #define CONFIG_ARCH_CPU_INIT 38 #define CONFIG_SETUP_MEMORY_TAGS 39 #define CONFIG_INITRD_TAG 40 #define CONFIG_SERIAL_TAG 41 #define CONFIG_REVISION_TAG 42 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 43 #define CONFIG_MISC_INIT_R /* Call misc_init_r */ 44 45 #define CONFIG_PREBOOT /* enable preboot variable */ 46 47 /* 48 * Hardware drivers 49 */ 50 51 /* 52 * BOOTP options 53 */ 54 #define CONFIG_BOOTP_BOOTFILESIZE 55 56 /* 57 * SDRAM: 1 bank, min 32, max 128 MB 58 * Initialized before u-boot gets started. 59 */ 60 #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ 61 #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */ 62 63 #define CONFIG_NR_DRAM_BANKS 1 64 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 65 #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE 66 67 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) 68 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000) 69 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000) 70 71 /* 72 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, 73 * leaving the correct space for initial global data structure above 74 * that address while providing maximum stack area below. 75 */ 76 #define CONFIG_SYS_INIT_SP_ADDR \ 77 (ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 78 79 /* NAND flash */ 80 #ifdef CONFIG_CMD_NAND 81 # define CONFIG_NAND_ATMEL 82 # define CONFIG_SYS_MAX_NAND_DEVICE 1 83 # define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ 84 # define CONFIG_SYS_NAND_DBW_8 85 # define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 86 # define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 87 # define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) 88 # define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) 89 #endif 90 91 /* Ethernet */ 92 #define CONFIG_MACB 93 #define CONFIG_RMII 94 #define CONFIG_NET_RETRY_COUNT 20 95 #undef CONFIG_RESET_PHY_R 96 97 /* hw-controller addresses */ 98 #define CONFIG_ET1100_BASE 0x70000000 99 100 #ifdef CONFIG_SYS_USE_DATAFLASH 101 102 /* bootstrap + u-boot + env in dataflash on CS0 */ 103 #define CONFIG_ENV_OFFSET 0x4200 104 #define CONFIG_ENV_SIZE 0x4200 105 #define CONFIG_ENV_SECT_SIZE 0x210 106 #define CONFIG_ENV_SPI_MAX_HZ 15000000 107 108 #elif CONFIG_SYS_USE_NANDFLASH 109 110 /* bootstrap + u-boot + env + linux in nandflash */ 111 # define CONFIG_ENV_OFFSET 0xC0000 112 # define CONFIG_ENV_SIZE 0x20000 113 114 #endif 115 116 #define CONFIG_SYS_CBSIZE 512 117 118 /* 119 * Size of malloc() pool 120 */ 121 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ 122 128*1024, 0x1000) 123 124 #endif 125