1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * (C) Copyright 2009-2015 7 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 8 * esd electronic system design gmbh <www.esd.eu> 9 * 10 * Configuation settings for the esd MEESC board. 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 /* 19 * SoC must be defined first, before hardware.h is included. 20 * In this case SoC is defined in boards.cfg. 21 */ 22 #include <asm/hardware.h> 23 24 /* 25 * Warning: changing CONFIG_SYS_TEXT_BASE requires 26 * adapting the initial boot program. 27 * Since the linker has to swallow that define, we must use a pure 28 * hex number here! 29 */ 30 31 /* ARM asynchronous clock */ 32 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ 33 #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ 34 35 /* Misc CPU related */ 36 #define CONFIG_SKIP_LOWLEVEL_INIT 37 #define CONFIG_ARCH_CPU_INIT 38 #define CONFIG_SETUP_MEMORY_TAGS 39 #define CONFIG_INITRD_TAG 40 #define CONFIG_SERIAL_TAG 41 #define CONFIG_REVISION_TAG 42 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 43 #define CONFIG_MISC_INIT_R /* Call misc_init_r */ 44 45 #define CONFIG_PREBOOT /* enable preboot variable */ 46 47 /* 48 * Hardware drivers 49 */ 50 51 /* 52 * BOOTP options 53 */ 54 #define CONFIG_BOOTP_BOOTFILESIZE 55 #define CONFIG_BOOTP_BOOTPATH 56 #define CONFIG_BOOTP_GATEWAY 57 #define CONFIG_BOOTP_HOSTNAME 58 59 /* 60 * SDRAM: 1 bank, min 32, max 128 MB 61 * Initialized before u-boot gets started. 62 */ 63 #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ 64 #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */ 65 66 #define CONFIG_NR_DRAM_BANKS 1 67 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 68 #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE 69 70 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) 71 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000) 72 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000) 73 74 /* 75 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, 76 * leaving the correct space for initial global data structure above 77 * that address while providing maximum stack area below. 78 */ 79 #define CONFIG_SYS_INIT_SP_ADDR \ 80 (ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 81 82 /* NAND flash */ 83 #ifdef CONFIG_CMD_NAND 84 # define CONFIG_NAND_ATMEL 85 # define CONFIG_SYS_MAX_NAND_DEVICE 1 86 # define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ 87 # define CONFIG_SYS_NAND_DBW_8 88 # define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 89 # define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 90 # define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) 91 # define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) 92 #endif 93 94 /* Ethernet */ 95 #define CONFIG_MACB 96 #define CONFIG_RMII 97 #define CONFIG_NET_RETRY_COUNT 20 98 #undef CONFIG_RESET_PHY_R 99 100 /* hw-controller addresses */ 101 #define CONFIG_ET1100_BASE 0x70000000 102 103 #ifdef CONFIG_SYS_USE_DATAFLASH 104 105 /* bootstrap + u-boot + env in dataflash on CS0 */ 106 #define CONFIG_ENV_OFFSET 0x4200 107 #define CONFIG_ENV_SIZE 0x4200 108 #define CONFIG_ENV_SECT_SIZE 0x210 109 #define CONFIG_ENV_SPI_MAX_HZ 15000000 110 111 #elif CONFIG_SYS_USE_NANDFLASH 112 113 /* bootstrap + u-boot + env + linux in nandflash */ 114 # define CONFIG_ENV_OFFSET 0xC0000 115 # define CONFIG_ENV_SIZE 0x20000 116 117 #endif 118 119 #define CONFIG_SYS_CBSIZE 512 120 #define CONFIG_SYS_LONGHELP 121 #define CONFIG_CMDLINE_EDITING 122 #define CONFIG_AUTO_COMPLETE 123 124 /* 125 * Size of malloc() pool 126 */ 127 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ 128 128*1024, 0x1000) 129 130 #endif 131