1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on omap3_evm_config.h 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_OMAP /* in a TI OMAP core */ 16 #define CONFIG_OMAP3_MCX /* working with mcx */ 17 #define CONFIG_OMAP_GPIO 18 #define CONFIG_OMAP_COMMON 19 /* Common ARM Erratas */ 20 #define CONFIG_ARM_ERRATA_454179 21 #define CONFIG_ARM_ERRATA_430973 22 #define CONFIG_ARM_ERRATA_621766 23 24 #define MACH_TYPE_MCX 3656 25 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 26 #define CONFIG_BOARD_LATE_INIT 27 28 #define CONFIG_SYS_GENERIC_BOARD 29 30 #define CONFIG_SYS_CACHELINE_SIZE 64 31 32 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 33 34 #include <asm/arch/cpu.h> /* get chip and board defs */ 35 #include <asm/arch/omap.h> 36 37 #define CONFIG_OF_LIBFDT 38 #define CONFIG_FIT 39 40 /* 41 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 42 * and older u-boot.bin with the new U-Boot SPL. 43 */ 44 #define CONFIG_SYS_TEXT_BASE 0x80008000 45 46 /* 47 * Display CPU and Board information 48 */ 49 #define CONFIG_DISPLAY_CPUINFO 50 #define CONFIG_DISPLAY_BOARDINFO 51 52 /* Clock Defines */ 53 #define V_OSCK 26000000 /* Clock output from T2 */ 54 #define V_SCLK (V_OSCK >> 1) 55 56 #define CONFIG_MISC_INIT_R 57 58 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 59 #define CONFIG_SETUP_MEMORY_TAGS 60 #define CONFIG_INITRD_TAG 61 #define CONFIG_REVISION_TAG 62 63 /* 64 * Size of malloc() pool 65 */ 66 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 67 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 68 /* 69 * DDR related 70 */ 71 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 72 73 /* 74 * Hardware drivers 75 */ 76 77 /* 78 * NS16550 Configuration 79 */ 80 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 81 82 #define CONFIG_SYS_NS16550 83 #define CONFIG_SYS_NS16550_SERIAL 84 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 85 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 86 87 /* 88 * select serial console configuration 89 */ 90 #define CONFIG_CONS_INDEX 3 91 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 92 #define CONFIG_SERIAL3 3 /* UART3 */ 93 94 /* allow to overwrite serial and ethaddr */ 95 #define CONFIG_ENV_OVERWRITE 96 #define CONFIG_BAUDRATE 115200 97 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 98 115200} 99 #define CONFIG_MMC 100 #define CONFIG_OMAP_HSMMC 101 #define CONFIG_GENERIC_MMC 102 #define CONFIG_DOS_PARTITION 103 104 /* EHCI */ 105 #define CONFIG_USB_STORAGE 106 #define CONFIG_OMAP3_GPIO_2 107 #define CONFIG_OMAP3_GPIO_5 108 #define CONFIG_USB_EHCI 109 #define CONFIG_USB_EHCI_OMAP 110 #define CONFIG_USB_ULPI 111 #define CONFIG_USB_ULPI_VIEWPORT_OMAP 112 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 113 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 114 #define CONFIG_USB_HOST_ETHER 115 #define CONFIG_USB_ETHER_ASIX 116 #define CONFIG_USB_ETHER_MCS7830 117 118 /* commands to include */ 119 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 120 #define CONFIG_CMD_FAT /* FAT support */ 121 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 122 123 #define CONFIG_CMD_DATE 124 #define CONFIG_CMD_I2C /* I2C serial bus support */ 125 #define CONFIG_CMD_MMC /* MMC support */ 126 #define CONFIG_CMD_FAT /* FAT support */ 127 #define CONFIG_CMD_USB 128 #define CONFIG_CMD_NAND /* NAND support */ 129 #define CONFIG_CMD_DHCP 130 #define CONFIG_CMD_PING 131 #define CONFIG_CMD_CACHE 132 #define CONFIG_CMD_UBI 133 #define CONFIG_CMD_UBIFS 134 #define CONFIG_RBTREE 135 #define CONFIG_LZO 136 #define CONFIG_MTD_PARTITIONS 137 #define CONFIG_MTD_DEVICE 138 #define CONFIG_CMD_MTDPARTS 139 #define CONFIG_CMD_GPIO 140 141 #define CONFIG_SYS_NO_FLASH 142 #define CONFIG_SYS_I2C 143 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 144 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 145 #define CONFIG_SYS_I2C_OMAP34XX 146 147 /* RTC */ 148 #define CONFIG_RTC_DS1337 149 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 150 151 #define CONFIG_CMD_MII 152 /* 153 * Board NAND Info. 154 */ 155 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 156 /* to access nand */ 157 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 158 /* to access */ 159 /* nand at CS0 */ 160 161 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 162 /* NAND devices */ 163 #define CONFIG_JFFS2_NAND 164 /* nand device jffs2 lives on */ 165 #define CONFIG_JFFS2_DEV "nand0" 166 /* start of jffs2 partition */ 167 #define CONFIG_JFFS2_PART_OFFSET 0x680000 168 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 169 170 /* Environment information */ 171 #define CONFIG_BOOTDELAY 3 172 173 #define CONFIG_BOOTFILE "uImage" 174 175 /* Setup MTD for NAND on the SOM */ 176 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 177 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 178 "1m(u-boot),256k(env1)," \ 179 "256k(env2),6m(kernel),6m(k_recovery)," \ 180 "8m(fs_recovery),-(common_data)" 181 182 #define CONFIG_HOSTNAME mcx 183 #define CONFIG_EXTRA_ENV_SETTINGS \ 184 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 185 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 186 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 187 "addfb=setenv bootargs ${bootargs} vram=6M " \ 188 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 189 "addip_sta=setenv bootargs ${bootargs} " \ 190 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 191 "${netmask}:${hostname}:eth0:off\0" \ 192 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 193 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 194 "else run addip_sta;fi\0" \ 195 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 196 "addtty=setenv bootargs ${bootargs} " \ 197 "console=${consoledev},${baudrate}\0" \ 198 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 199 "baudrate=115200\0" \ 200 "consoledev=ttyO2\0" \ 201 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 202 "loadaddr=0x82000000\0" \ 203 "load=tftp ${loadaddr} ${u-boot}\0" \ 204 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 205 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 206 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 207 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 208 "mmcargs=root=/dev/mmcblk0p2 rw " \ 209 "rootfstype=ext3 rootwait\0" \ 210 "mmcboot=echo Booting from mmc ...; " \ 211 "run mmcargs; " \ 212 "run addip addtty addmtd addfb addeth addmisc;" \ 213 "run loaduimage; " \ 214 "bootm ${loadaddr}\0" \ 215 "net_nfs=run load_k; " \ 216 "run nfsargs; " \ 217 "run addip addtty addmtd addfb addeth addmisc;" \ 218 "bootm ${loadaddr}\0" \ 219 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 220 "nfsroot=${serverip}:${rootpath}\0" \ 221 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 222 "uboot_addr=0x80000\0" \ 223 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 224 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 225 "updatemlo=nandecc hw;nand erase 0 20000;" \ 226 "nand write ${loadaddr} 0 20000\0" \ 227 "upd=if run load;then echo Updating u-boot;if run update;" \ 228 "then echo U-Boot updated;" \ 229 "else echo Error updating u-boot !;" \ 230 "echo Board without bootloader !!;" \ 231 "fi;" \ 232 "else echo U-Boot not downloaded..exiting;fi\0" \ 233 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 234 "bootscript=echo Running bootscript from mmc ...; " \ 235 "source ${loadaddr}\0" \ 236 "nandargs=setenv bootargs ubi.mtd=7 " \ 237 "root=ubi0:rootfs rootfstype=ubifs\0" \ 238 "nandboot=echo Booting from nand ...; " \ 239 "run nandargs; " \ 240 "ubi part nand0,4;" \ 241 "ubi readvol ${loadaddr} kernel;" \ 242 "run addtty addmtd addfb addeth addmisc;" \ 243 "bootm ${loadaddr}\0" \ 244 "preboot=ubi part nand0,7;" \ 245 "ubi readvol ${loadaddr} splash;" \ 246 "bmp display ${loadaddr};" \ 247 "gpio set 55\0" \ 248 "swupdate_args=setenv bootargs root=/dev/ram " \ 249 "quiet loglevel=1 " \ 250 "consoleblank=0 ${swupdate_misc}\0" \ 251 "swupdate=echo Running Sw-Update...;" \ 252 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 253 "else mtdparts default;fi; " \ 254 "ubi part nand0,5;" \ 255 "ubi readvol 0x82000000 kernel_recovery;" \ 256 "ubi part nand0,6;" \ 257 "ubi readvol 0x84000000 fs_recovery;" \ 258 "run swupdate_args; " \ 259 "setenv bootargs ${bootargs} " \ 260 "${mtdparts} " \ 261 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 262 "omapdss.def_disp=lcd;" \ 263 "bootm 0x82000000 0x84000000\0" \ 264 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 265 "then source 82000000;else run nandboot;fi\0" 266 267 #define CONFIG_AUTO_COMPLETE 268 #define CONFIG_CMDLINE_EDITING 269 270 /* 271 * Miscellaneous configurable options 272 */ 273 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 274 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 275 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 276 /* Print Buffer Size */ 277 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 278 sizeof(CONFIG_SYS_PROMPT) + 16) 279 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 280 /* args */ 281 /* Boot Argument Buffer Size */ 282 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 283 /* memtest works on */ 284 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 285 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 286 0x01F00000) /* 31MB */ 287 288 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 289 /* address */ 290 #define CONFIG_PREBOOT 291 292 /* 293 * AM3517 has 12 GP timers, they can be driven by the system clock 294 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 295 * This rate is divided by a local divisor. 296 */ 297 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 298 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 299 300 /* 301 * Physical Memory Map 302 */ 303 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 304 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 305 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 306 307 /* 308 * FLASH and environment organization 309 */ 310 311 /* **** PISMO SUPPORT *** */ 312 #define CONFIG_NAND 313 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 314 #define CONFIG_NAND_OMAP_GPMC 315 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 316 #define CONFIG_ENV_IS_IN_NAND 317 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 318 319 /* Redundant Environment */ 320 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 321 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 322 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 323 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 324 2 * CONFIG_SYS_ENV_SECT_SIZE) 325 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 326 327 /* Flash banks JFFS2 should use */ 328 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 329 CONFIG_SYS_MAX_NAND_DEVICE) 330 #define CONFIG_SYS_JFFS2_MEM_NAND 331 /* use flash_info[2] */ 332 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 333 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 334 335 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 336 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 337 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 338 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 339 CONFIG_SYS_INIT_RAM_SIZE - \ 340 GENERATED_GBL_DATA_SIZE) 341 342 /* Defines for SPL */ 343 #define CONFIG_SPL_FRAMEWORK 344 #define CONFIG_SPL_BOARD_INIT 345 #define CONFIG_SPL_NAND_SIMPLE 346 347 #define CONFIG_SPL_LIBCOMMON_SUPPORT 348 #define CONFIG_SPL_LIBDISK_SUPPORT 349 #define CONFIG_SPL_I2C_SUPPORT 350 #define CONFIG_SPL_MMC_SUPPORT 351 #define CONFIG_SPL_FAT_SUPPORT 352 #define CONFIG_SPL_LIBGENERIC_SUPPORT 353 #define CONFIG_SPL_SERIAL_SUPPORT 354 #define CONFIG_SPL_POWER_SUPPORT 355 #define CONFIG_SPL_NAND_SUPPORT 356 #define CONFIG_SPL_NAND_BASE 357 #define CONFIG_SPL_NAND_DRIVERS 358 #define CONFIG_SPL_NAND_ECC 359 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 360 361 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 362 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 363 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 364 365 /* move malloc and bss high to prevent clashing with the main image */ 366 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 367 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 368 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 369 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 370 371 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 372 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 373 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 374 375 /* NAND boot config */ 376 #define CONFIG_SYS_NAND_PAGE_COUNT 64 377 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 378 #define CONFIG_SYS_NAND_OOBSIZE 64 379 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 380 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 381 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 382 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 383 48, 49, 50, 51, 52, 53, 54, 55,\ 384 56, 57, 58, 59, 60, 61, 62, 63} 385 #define CONFIG_SYS_NAND_ECCSIZE 256 386 #define CONFIG_SYS_NAND_ECCBYTES 3 387 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 388 #define CONFIG_SPL_NAND_SOFTECC 389 390 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 391 392 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 393 394 /* 395 * ethernet support 396 * 397 */ 398 #if defined(CONFIG_CMD_NET) 399 #define CONFIG_DRIVER_TI_EMAC 400 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 401 #define CONFIG_MII 402 #define CONFIG_BOOTP_DNS 403 #define CONFIG_BOOTP_DNS2 404 #define CONFIG_BOOTP_SEND_HOSTNAME 405 #define CONFIG_NET_RETRY_COUNT 10 406 #endif 407 408 #define CONFIG_VIDEO 409 #define CONFIG_CFB_CONSOLE 410 #define CONFIG_VGA_AS_SINGLE_DEVICE 411 #define CONFIG_SPLASH_SCREEN 412 #define CONFIG_VIDEO_BMP_RLE8 413 #define CONFIG_CMD_BMP 414 #define CONFIG_VIDEO_OMAP3 415 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 416 417 #endif /* __CONFIG_H */ 418