1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on omap3_evm_config.h 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_OMAP /* in a TI OMAP core */ 16 #define CONFIG_OMAP3_MCX /* working with mcx */ 17 #define CONFIG_OMAP_GPIO 18 #define CONFIG_OMAP_COMMON 19 /* Common ARM Erratas */ 20 #define CONFIG_ARM_ERRATA_454179 21 #define CONFIG_ARM_ERRATA_430973 22 #define CONFIG_ARM_ERRATA_621766 23 24 #define MACH_TYPE_MCX 3656 25 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 26 #define CONFIG_BOARD_LATE_INIT 27 28 #define CONFIG_SYS_CACHELINE_SIZE 64 29 30 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 31 32 #include <asm/arch/cpu.h> /* get chip and board defs */ 33 #include <asm/arch/omap.h> 34 35 /* 36 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 37 * and older u-boot.bin with the new U-Boot SPL. 38 */ 39 #define CONFIG_SYS_TEXT_BASE 0x80008000 40 41 /* 42 * Display CPU and Board information 43 */ 44 #define CONFIG_DISPLAY_CPUINFO 45 #define CONFIG_DISPLAY_BOARDINFO 46 47 /* Clock Defines */ 48 #define V_OSCK 26000000 /* Clock output from T2 */ 49 #define V_SCLK (V_OSCK >> 1) 50 51 #define CONFIG_MISC_INIT_R 52 53 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 54 #define CONFIG_SETUP_MEMORY_TAGS 55 #define CONFIG_INITRD_TAG 56 #define CONFIG_REVISION_TAG 57 58 /* 59 * Size of malloc() pool 60 */ 61 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 62 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 63 /* 64 * DDR related 65 */ 66 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 67 68 /* 69 * Hardware drivers 70 */ 71 72 /* 73 * NS16550 Configuration 74 */ 75 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 76 77 #define CONFIG_SYS_NS16550_SERIAL 78 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 79 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 80 81 /* 82 * select serial console configuration 83 */ 84 #define CONFIG_CONS_INDEX 3 85 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 86 #define CONFIG_SERIAL3 3 /* UART3 */ 87 88 /* allow to overwrite serial and ethaddr */ 89 #define CONFIG_ENV_OVERWRITE 90 #define CONFIG_BAUDRATE 115200 91 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 92 115200} 93 #define CONFIG_MMC 94 #define CONFIG_OMAP_HSMMC 95 #define CONFIG_GENERIC_MMC 96 #define CONFIG_DOS_PARTITION 97 98 /* EHCI */ 99 #define CONFIG_USB_STORAGE 100 #define CONFIG_OMAP3_GPIO_2 101 #define CONFIG_OMAP3_GPIO_5 102 #define CONFIG_USB_EHCI 103 #define CONFIG_USB_EHCI_OMAP 104 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 105 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 106 #define CONFIG_USB_HOST_ETHER 107 #define CONFIG_USB_ETHER_ASIX 108 #define CONFIG_USB_ETHER_MCS7830 109 110 /* commands to include */ 111 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 112 113 #define CONFIG_CMD_DATE 114 #define CONFIG_CMD_NAND /* NAND support */ 115 #define CONFIG_CMD_UBI 116 #define CONFIG_CMD_UBIFS 117 #define CONFIG_RBTREE 118 #define CONFIG_LZO 119 #define CONFIG_MTD_PARTITIONS 120 #define CONFIG_MTD_DEVICE 121 #define CONFIG_CMD_MTDPARTS 122 123 #define CONFIG_SYS_NO_FLASH 124 #define CONFIG_SYS_I2C 125 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 126 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 127 #define CONFIG_SYS_I2C_OMAP34XX 128 129 /* RTC */ 130 #define CONFIG_RTC_DS1337 131 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 132 133 /* 134 * Board NAND Info. 135 */ 136 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 137 /* to access nand */ 138 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 139 /* to access */ 140 /* nand at CS0 */ 141 142 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 143 /* NAND devices */ 144 #define CONFIG_JFFS2_NAND 145 /* nand device jffs2 lives on */ 146 #define CONFIG_JFFS2_DEV "nand0" 147 /* start of jffs2 partition */ 148 #define CONFIG_JFFS2_PART_OFFSET 0x680000 149 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 150 151 /* Environment information */ 152 #define CONFIG_BOOTDELAY 3 153 154 #define CONFIG_BOOTFILE "uImage" 155 156 /* Setup MTD for NAND on the SOM */ 157 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 158 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 159 "1m(u-boot),256k(env1)," \ 160 "256k(env2),6m(kernel),6m(k_recovery)," \ 161 "8m(fs_recovery),-(common_data)" 162 163 #define CONFIG_HOSTNAME mcx 164 #define CONFIG_EXTRA_ENV_SETTINGS \ 165 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 166 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 167 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 168 "addfb=setenv bootargs ${bootargs} vram=6M " \ 169 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 170 "addip_sta=setenv bootargs ${bootargs} " \ 171 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 172 "${netmask}:${hostname}:eth0:off\0" \ 173 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 174 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 175 "else run addip_sta;fi\0" \ 176 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 177 "addtty=setenv bootargs ${bootargs} " \ 178 "console=${consoledev},${baudrate}\0" \ 179 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 180 "baudrate=115200\0" \ 181 "consoledev=ttyO2\0" \ 182 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 183 "loadaddr=0x82000000\0" \ 184 "load=tftp ${loadaddr} ${u-boot}\0" \ 185 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 186 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 187 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 188 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 189 "mmcargs=root=/dev/mmcblk0p2 rw " \ 190 "rootfstype=ext3 rootwait\0" \ 191 "mmcboot=echo Booting from mmc ...; " \ 192 "run mmcargs; " \ 193 "run addip addtty addmtd addfb addeth addmisc;" \ 194 "run loaduimage; " \ 195 "bootm ${loadaddr}\0" \ 196 "net_nfs=run load_k; " \ 197 "run nfsargs; " \ 198 "run addip addtty addmtd addfb addeth addmisc;" \ 199 "bootm ${loadaddr}\0" \ 200 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 201 "nfsroot=${serverip}:${rootpath}\0" \ 202 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 203 "uboot_addr=0x80000\0" \ 204 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 205 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 206 "updatemlo=nandecc hw;nand erase 0 20000;" \ 207 "nand write ${loadaddr} 0 20000\0" \ 208 "upd=if run load;then echo Updating u-boot;if run update;" \ 209 "then echo U-Boot updated;" \ 210 "else echo Error updating u-boot !;" \ 211 "echo Board without bootloader !!;" \ 212 "fi;" \ 213 "else echo U-Boot not downloaded..exiting;fi\0" \ 214 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 215 "bootscript=echo Running bootscript from mmc ...; " \ 216 "source ${loadaddr}\0" \ 217 "nandargs=setenv bootargs ubi.mtd=7 " \ 218 "root=ubi0:rootfs rootfstype=ubifs\0" \ 219 "nandboot=echo Booting from nand ...; " \ 220 "run nandargs; " \ 221 "ubi part nand0,4;" \ 222 "ubi readvol ${loadaddr} kernel;" \ 223 "run addtty addmtd addfb addeth addmisc;" \ 224 "bootm ${loadaddr}\0" \ 225 "preboot=ubi part nand0,7;" \ 226 "ubi readvol ${loadaddr} splash;" \ 227 "bmp display ${loadaddr};" \ 228 "gpio set 55\0" \ 229 "swupdate_args=setenv bootargs root=/dev/ram " \ 230 "quiet loglevel=1 " \ 231 "consoleblank=0 ${swupdate_misc}\0" \ 232 "swupdate=echo Running Sw-Update...;" \ 233 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 234 "else mtdparts default;fi; " \ 235 "ubi part nand0,5;" \ 236 "ubi readvol 0x82000000 kernel_recovery;" \ 237 "ubi part nand0,6;" \ 238 "ubi readvol 0x84000000 fs_recovery;" \ 239 "run swupdate_args; " \ 240 "setenv bootargs ${bootargs} " \ 241 "${mtdparts} " \ 242 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 243 "omapdss.def_disp=lcd;" \ 244 "bootm 0x82000000 0x84000000\0" \ 245 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 246 "then source 82000000;else run nandboot;fi\0" 247 248 #define CONFIG_AUTO_COMPLETE 249 #define CONFIG_CMDLINE_EDITING 250 251 /* 252 * Miscellaneous configurable options 253 */ 254 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 255 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 256 /* Print Buffer Size */ 257 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 258 sizeof(CONFIG_SYS_PROMPT) + 16) 259 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 260 /* args */ 261 /* Boot Argument Buffer Size */ 262 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 263 /* memtest works on */ 264 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 265 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 266 0x01F00000) /* 31MB */ 267 268 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 269 /* address */ 270 #define CONFIG_PREBOOT 271 272 /* 273 * AM3517 has 12 GP timers, they can be driven by the system clock 274 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 275 * This rate is divided by a local divisor. 276 */ 277 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 278 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 279 280 /* 281 * Physical Memory Map 282 */ 283 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 284 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 285 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 286 287 /* 288 * FLASH and environment organization 289 */ 290 291 /* **** PISMO SUPPORT *** */ 292 #define CONFIG_NAND 293 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 294 #define CONFIG_NAND_OMAP_GPMC 295 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 296 #define CONFIG_ENV_IS_IN_NAND 297 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 298 299 /* Redundant Environment */ 300 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 301 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 302 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 303 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 304 2 * CONFIG_SYS_ENV_SECT_SIZE) 305 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 306 307 /* Flash banks JFFS2 should use */ 308 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 309 CONFIG_SYS_MAX_NAND_DEVICE) 310 #define CONFIG_SYS_JFFS2_MEM_NAND 311 /* use flash_info[2] */ 312 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 313 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 314 315 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 316 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 317 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 318 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 319 CONFIG_SYS_INIT_RAM_SIZE - \ 320 GENERATED_GBL_DATA_SIZE) 321 322 /* Defines for SPL */ 323 #define CONFIG_SPL_FRAMEWORK 324 #define CONFIG_SPL_BOARD_INIT 325 #define CONFIG_SPL_NAND_SIMPLE 326 327 #define CONFIG_SPL_LIBCOMMON_SUPPORT 328 #define CONFIG_SPL_LIBDISK_SUPPORT 329 #define CONFIG_SPL_I2C_SUPPORT 330 #define CONFIG_SPL_MMC_SUPPORT 331 #define CONFIG_SPL_FAT_SUPPORT 332 #define CONFIG_SPL_LIBGENERIC_SUPPORT 333 #define CONFIG_SPL_SERIAL_SUPPORT 334 #define CONFIG_SPL_POWER_SUPPORT 335 #define CONFIG_SPL_NAND_SUPPORT 336 #define CONFIG_SPL_NAND_BASE 337 #define CONFIG_SPL_NAND_DRIVERS 338 #define CONFIG_SPL_NAND_ECC 339 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 340 341 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 342 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 343 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 344 345 /* move malloc and bss high to prevent clashing with the main image */ 346 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 347 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 348 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 349 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 350 351 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 352 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 353 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 354 355 /* NAND boot config */ 356 #define CONFIG_SYS_NAND_PAGE_COUNT 64 357 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 358 #define CONFIG_SYS_NAND_OOBSIZE 64 359 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 360 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 361 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 362 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 363 48, 49, 50, 51, 52, 53, 54, 55,\ 364 56, 57, 58, 59, 60, 61, 62, 63} 365 #define CONFIG_SYS_NAND_ECCSIZE 256 366 #define CONFIG_SYS_NAND_ECCBYTES 3 367 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 368 #define CONFIG_SPL_NAND_SOFTECC 369 370 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 371 372 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 373 374 /* 375 * ethernet support 376 * 377 */ 378 #if defined(CONFIG_CMD_NET) 379 #define CONFIG_DRIVER_TI_EMAC 380 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 381 #define CONFIG_MII 382 #define CONFIG_BOOTP_DNS 383 #define CONFIG_BOOTP_DNS2 384 #define CONFIG_BOOTP_SEND_HOSTNAME 385 #define CONFIG_NET_RETRY_COUNT 10 386 #endif 387 388 #define CONFIG_VIDEO 389 #define CONFIG_CFB_CONSOLE 390 #define CONFIG_VGA_AS_SINGLE_DEVICE 391 #define CONFIG_SPLASH_SCREEN 392 #define CONFIG_VIDEO_BMP_RLE8 393 #define CONFIG_CMD_BMP 394 #define CONFIG_VIDEO_OMAP3 395 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 396 397 #endif /* __CONFIG_H */ 398