1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on omap3_evm_config.h 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 16 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 17 18 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 19 20 #include <asm/arch/cpu.h> /* get chip and board defs */ 21 #include <asm/arch/omap.h> 22 23 /* 24 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 25 * and older u-boot.bin with the new U-Boot SPL. 26 */ 27 #define CONFIG_SYS_TEXT_BASE 0x80008000 28 29 /* Clock Defines */ 30 #define V_OSCK 26000000 /* Clock output from T2 */ 31 #define V_SCLK (V_OSCK >> 1) 32 33 #define CONFIG_MISC_INIT_R 34 35 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 36 #define CONFIG_SETUP_MEMORY_TAGS 37 #define CONFIG_INITRD_TAG 38 #define CONFIG_REVISION_TAG 39 40 /* 41 * Size of malloc() pool 42 */ 43 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 44 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 45 /* 46 * DDR related 47 */ 48 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 49 50 /* 51 * Hardware drivers 52 */ 53 54 /* 55 * NS16550 Configuration 56 */ 57 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 58 59 #define CONFIG_SYS_NS16550_SERIAL 60 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 61 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 62 63 /* 64 * select serial console configuration 65 */ 66 #define CONFIG_CONS_INDEX 3 67 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 68 #define CONFIG_SERIAL3 3 /* UART3 */ 69 70 /* allow to overwrite serial and ethaddr */ 71 #define CONFIG_ENV_OVERWRITE 72 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 73 115200} 74 75 /* EHCI */ 76 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 77 78 /* commands to include */ 79 80 #define CONFIG_MTD_PARTITIONS 81 #define CONFIG_MTD_DEVICE 82 83 #define CONFIG_SYS_I2C 84 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 85 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 86 87 /* RTC */ 88 #define CONFIG_RTC_DS1337 89 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 90 91 /* 92 * Board NAND Info. 93 */ 94 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 95 /* to access nand */ 96 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 97 /* to access */ 98 /* nand at CS0 */ 99 100 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 101 /* NAND devices */ 102 #define CONFIG_JFFS2_NAND 103 /* nand device jffs2 lives on */ 104 #define CONFIG_JFFS2_DEV "nand0" 105 /* start of jffs2 partition */ 106 #define CONFIG_JFFS2_PART_OFFSET 0x680000 107 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 108 109 /* Environment information */ 110 111 #define CONFIG_BOOTFILE "uImage" 112 113 /* Setup MTD for NAND on the SOM */ 114 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 115 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 116 "1m(u-boot),256k(env1)," \ 117 "256k(env2),6m(kernel),6m(k_recovery)," \ 118 "8m(fs_recovery),-(common_data)" 119 120 #define CONFIG_HOSTNAME mcx 121 #define CONFIG_EXTRA_ENV_SETTINGS \ 122 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 123 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 124 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 125 "addfb=setenv bootargs ${bootargs} vram=6M " \ 126 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 127 "addip_sta=setenv bootargs ${bootargs} " \ 128 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 129 "${netmask}:${hostname}:eth0:off\0" \ 130 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 131 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 132 "else run addip_sta;fi\0" \ 133 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 134 "addtty=setenv bootargs ${bootargs} " \ 135 "console=${consoledev},${baudrate}\0" \ 136 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 137 "baudrate=115200\0" \ 138 "consoledev=ttyO2\0" \ 139 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 140 "loadaddr=0x82000000\0" \ 141 "load=tftp ${loadaddr} ${u-boot}\0" \ 142 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 143 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 144 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 145 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 146 "mmcargs=root=/dev/mmcblk0p2 rw " \ 147 "rootfstype=ext3 rootwait\0" \ 148 "mmcboot=echo Booting from mmc ...; " \ 149 "run mmcargs; " \ 150 "run addip addtty addmtd addfb addeth addmisc;" \ 151 "run loaduimage; " \ 152 "bootm ${loadaddr}\0" \ 153 "net_nfs=run load_k; " \ 154 "run nfsargs; " \ 155 "run addip addtty addmtd addfb addeth addmisc;" \ 156 "bootm ${loadaddr}\0" \ 157 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 158 "nfsroot=${serverip}:${rootpath}\0" \ 159 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 160 "uboot_addr=0x80000\0" \ 161 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 162 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 163 "updatemlo=nandecc hw;nand erase 0 20000;" \ 164 "nand write ${loadaddr} 0 20000\0" \ 165 "upd=if run load;then echo Updating u-boot;if run update;" \ 166 "then echo U-Boot updated;" \ 167 "else echo Error updating u-boot !;" \ 168 "echo Board without bootloader !!;" \ 169 "fi;" \ 170 "else echo U-Boot not downloaded..exiting;fi\0" \ 171 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 172 "bootscript=echo Running bootscript from mmc ...; " \ 173 "source ${loadaddr}\0" \ 174 "nandargs=setenv bootargs ubi.mtd=7 " \ 175 "root=ubi0:rootfs rootfstype=ubifs\0" \ 176 "nandboot=echo Booting from nand ...; " \ 177 "run nandargs; " \ 178 "ubi part nand0,4;" \ 179 "ubi readvol ${loadaddr} kernel;" \ 180 "run addtty addmtd addfb addeth addmisc;" \ 181 "bootm ${loadaddr}\0" \ 182 "preboot=ubi part nand0,7;" \ 183 "ubi readvol ${loadaddr} splash;" \ 184 "bmp display ${loadaddr};" \ 185 "gpio set 55\0" \ 186 "swupdate_args=setenv bootargs root=/dev/ram " \ 187 "quiet loglevel=1 " \ 188 "consoleblank=0 ${swupdate_misc}\0" \ 189 "swupdate=echo Running Sw-Update...;" \ 190 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 191 "else mtdparts default;fi; " \ 192 "ubi part nand0,5;" \ 193 "ubi readvol 0x82000000 kernel_recovery;" \ 194 "ubi part nand0,6;" \ 195 "ubi readvol 0x84000000 fs_recovery;" \ 196 "run swupdate_args; " \ 197 "setenv bootargs ${bootargs} " \ 198 "${mtdparts} " \ 199 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 200 "omapdss.def_disp=lcd;" \ 201 "bootm 0x82000000 0x84000000\0" \ 202 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 203 "then source 82000000;else run nandboot;fi\0" 204 205 #define CONFIG_AUTO_COMPLETE 206 #define CONFIG_CMDLINE_EDITING 207 208 /* 209 * Miscellaneous configurable options 210 */ 211 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 212 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 213 /* Boot Argument Buffer Size */ 214 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 215 /* memtest works on */ 216 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 217 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 218 0x01F00000) /* 31MB */ 219 220 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 221 /* address */ 222 #define CONFIG_PREBOOT 223 224 /* 225 * AM3517 has 12 GP timers, they can be driven by the system clock 226 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 227 * This rate is divided by a local divisor. 228 */ 229 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 230 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 231 232 /* 233 * Physical Memory Map 234 */ 235 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 236 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 237 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 238 239 /* 240 * FLASH and environment organization 241 */ 242 243 /* **** PISMO SUPPORT *** */ 244 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 245 #define CONFIG_NAND_OMAP_GPMC 246 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 247 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 248 249 /* Redundant Environment */ 250 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 251 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 252 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 253 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 254 2 * CONFIG_SYS_ENV_SECT_SIZE) 255 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 256 257 /* Flash banks JFFS2 should use */ 258 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 259 CONFIG_SYS_MAX_NAND_DEVICE) 260 #define CONFIG_SYS_JFFS2_MEM_NAND 261 /* use flash_info[2] */ 262 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 263 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 264 265 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 266 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 267 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 268 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 269 CONFIG_SYS_INIT_RAM_SIZE - \ 270 GENERATED_GBL_DATA_SIZE) 271 272 /* Defines for SPL */ 273 #define CONFIG_SPL_FRAMEWORK 274 #define CONFIG_SPL_NAND_SIMPLE 275 276 #define CONFIG_SPL_NAND_BASE 277 #define CONFIG_SPL_NAND_DRIVERS 278 #define CONFIG_SPL_NAND_ECC 279 280 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 281 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 282 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 283 284 /* move malloc and bss high to prevent clashing with the main image */ 285 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 286 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 287 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 288 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 289 290 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 291 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 292 293 /* NAND boot config */ 294 #define CONFIG_SYS_NAND_PAGE_COUNT 64 295 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 296 #define CONFIG_SYS_NAND_OOBSIZE 64 297 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 298 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 299 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 300 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 301 48, 49, 50, 51, 52, 53, 54, 55,\ 302 56, 57, 58, 59, 60, 61, 62, 63} 303 #define CONFIG_SYS_NAND_ECCSIZE 256 304 #define CONFIG_SYS_NAND_ECCBYTES 3 305 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 306 #define CONFIG_SPL_NAND_SOFTECC 307 308 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 309 310 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 311 312 /* 313 * ethernet support 314 * 315 */ 316 #if defined(CONFIG_CMD_NET) 317 #define CONFIG_DRIVER_TI_EMAC 318 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 319 #define CONFIG_MII 320 #define CONFIG_BOOTP_DNS 321 #define CONFIG_BOOTP_DNS2 322 #define CONFIG_BOOTP_SEND_HOSTNAME 323 #define CONFIG_NET_RETRY_COUNT 10 324 #endif 325 326 #define CONFIG_SPLASH_SCREEN 327 #define CONFIG_VIDEO_BMP_RLE8 328 #define CONFIG_VIDEO_OMAP3 329 330 #endif /* __CONFIG_H */ 331