xref: /openbmc/u-boot/include/configs/mcx.h (revision cc8fb2f7)
1 /*
2  * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
3  *
4  * Based on omap3_evm_config.h
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 /*
13  * High Level Configuration Options
14  */
15 
16 #define CONFIG_MACH_TYPE	MACH_TYPE_MCX
17 
18 #include <asm/arch/cpu.h>		/* get chip and board defs */
19 #include <asm/arch/omap.h>
20 
21 /*
22  * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
23  * and older u-boot.bin with the new U-Boot SPL.
24  */
25 #define CONFIG_SYS_TEXT_BASE		0x80008000
26 
27 /* Clock Defines */
28 #define V_OSCK			26000000	/* Clock output from T2 */
29 #define V_SCLK			(V_OSCK >> 1)
30 
31 #define CONFIG_MISC_INIT_R
32 
33 #define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
34 #define CONFIG_SETUP_MEMORY_TAGS
35 #define CONFIG_INITRD_TAG
36 #define CONFIG_REVISION_TAG
37 
38 /*
39  * Size of malloc() pool
40  */
41 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
42 #define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
43 /*
44  * DDR related
45  */
46 #define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
47 
48 /*
49  * Hardware drivers
50  */
51 
52 /*
53  * NS16550 Configuration
54  */
55 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
56 
57 #define CONFIG_SYS_NS16550_SERIAL
58 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
59 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
60 
61 /*
62  * select serial console configuration
63  */
64 #define CONFIG_CONS_INDEX		3
65 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
66 #define CONFIG_SERIAL3			3	/* UART3 */
67 
68 /* allow to overwrite serial and ethaddr */
69 #define CONFIG_ENV_OVERWRITE
70 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
71 					115200}
72 
73 /* EHCI */
74 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	57
75 
76 /* commands to include */
77 
78 #define CONFIG_MTD_PARTITIONS
79 #define CONFIG_MTD_DEVICE
80 
81 #define CONFIG_SYS_I2C
82 #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
83 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
84 
85 /* RTC */
86 #define CONFIG_RTC_DS1337
87 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
88 
89 /*
90  * Board NAND Info.
91  */
92 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
93 							/* to access nand */
94 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
95 							/* to access */
96 							/* nand at CS0 */
97 
98 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
99 							/* NAND devices */
100 #define CONFIG_JFFS2_NAND
101 /* nand device jffs2 lives on */
102 #define CONFIG_JFFS2_DEV		"nand0"
103 /* start of jffs2 partition */
104 #define CONFIG_JFFS2_PART_OFFSET	0x680000
105 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
106 
107 /* Environment information */
108 
109 #define CONFIG_BOOTFILE		"uImage"
110 
111 /* Setup MTD for NAND on the SOM */
112 #define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
113 #define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO),"	\
114 				"1m(u-boot),256k(env1),"		\
115 				"256k(env2),6m(kernel),6m(k_recovery),"	\
116 				"8m(fs_recovery),-(common_data)"
117 
118 #define CONFIG_HOSTNAME mcx
119 #define CONFIG_EXTRA_ENV_SETTINGS \
120 	"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0"	\
121 	"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0"	\
122 	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
123 	"addfb=setenv bootargs ${bootargs} vram=6M "			\
124 		"omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0"	\
125 	"addip_sta=setenv bootargs ${bootargs} "			\
126 		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
127 		"${netmask}:${hostname}:eth0:off\0"			\
128 	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
129 	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
130 		"else run addip_sta;fi\0"				\
131 	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
132 	"addtty=setenv bootargs ${bootargs} "				\
133 		"console=${consoledev},${baudrate}\0"			\
134 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
135 	"baudrate=115200\0"						\
136 	"consoledev=ttyO2\0"						\
137 	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
138 	"loadaddr=0x82000000\0"						\
139 	"load=tftp ${loadaddr} ${u-boot}\0"				\
140 	"load_k=tftp ${loadaddr} ${bootfile}\0"				\
141 	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0"			\
142 	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
143 	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
144 	"mmcargs=root=/dev/mmcblk0p2 rw "				\
145 		"rootfstype=ext3 rootwait\0"				\
146 	"mmcboot=echo Booting from mmc ...; "				\
147 		"run mmcargs; "						\
148 		"run addip addtty addmtd addfb addeth addmisc;"		\
149 		"run loaduimage; "					\
150 		"bootm ${loadaddr}\0"					\
151 	"net_nfs=run load_k; "						\
152 		"run nfsargs; "						\
153 		"run addip addtty addmtd addfb addeth addmisc;"		\
154 		"bootm ${loadaddr}\0"					\
155 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
156 		"nfsroot=${serverip}:${rootpath}\0"			\
157 	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
158 	"uboot_addr=0x80000\0"						\
159 	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
160 		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
161 	"updatemlo=nandecc hw;nand erase 0 20000;"			\
162 		"nand write ${loadaddr} 0 20000\0"			\
163 	"upd=if run load;then echo Updating u-boot;if run update;"	\
164 		"then echo U-Boot updated;"				\
165 			"else echo Error updating u-boot !;"		\
166 			"echo Board without bootloader !!;"		\
167 		"fi;"							\
168 		"else echo U-Boot not downloaded..exiting;fi\0"		\
169 	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0"		\
170 	"bootscript=echo Running bootscript from mmc ...; "		\
171 		"source ${loadaddr}\0"					\
172 	"nandargs=setenv bootargs ubi.mtd=7 "				\
173 		"root=ubi0:rootfs rootfstype=ubifs\0"			\
174 	"nandboot=echo Booting from nand ...; "				\
175 		"run nandargs; "					\
176 		"ubi part nand0,4;"					\
177 		"ubi readvol ${loadaddr} kernel;"			\
178 		"run addtty addmtd addfb addeth addmisc;"		\
179 		"bootm ${loadaddr}\0"					\
180 	"preboot=ubi part nand0,7;"					\
181 		"ubi readvol ${loadaddr} splash;"			\
182 		"bmp display ${loadaddr};"				\
183 		"gpio set 55\0"						\
184 	"swupdate_args=setenv bootargs root=/dev/ram "			\
185 		"quiet loglevel=1 "					\
186 		"consoleblank=0 ${swupdate_misc}\0"			\
187 	"swupdate=echo Running Sw-Update...;"				\
188 		"if printenv mtdparts;then echo Starting SwUpdate...; "	\
189 		"else mtdparts default;fi; "				\
190 		"ubi part nand0,5;"					\
191 		"ubi readvol 0x82000000 kernel_recovery;"		\
192 		"ubi part nand0,6;"					\
193 		"ubi readvol 0x84000000 fs_recovery;"			\
194 		"run swupdate_args; "					\
195 		"setenv bootargs ${bootargs} "				\
196 			"${mtdparts} "					\
197 			"vram=6M omapfb.vram=1:2M,2:2M,3:2M "		\
198 			"omapdss.def_disp=lcd;"				\
199 		"bootm 0x82000000 0x84000000\0"				\
200 	"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;"	\
201 		"then source 82000000;else run nandboot;fi\0"
202 
203 #define CONFIG_AUTO_COMPLETE
204 #define CONFIG_CMDLINE_EDITING
205 
206 /*
207  * Miscellaneous configurable options
208  */
209 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
210 #define CONFIG_SYS_CBSIZE		1024/* Console I/O Buffer Size */
211 /* Boot Argument Buffer Size */
212 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
213 /* memtest works on */
214 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
215 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
216 					0x01F00000) /* 31MB */
217 
218 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
219 								/* address */
220 #define CONFIG_PREBOOT
221 
222 /*
223  * AM3517 has 12 GP timers, they can be driven by the system clock
224  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
225  * This rate is divided by a local divisor.
226  */
227 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
228 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
229 
230 /*
231  * Physical Memory Map
232  */
233 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
234 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
235 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
236 
237 /*
238  * FLASH and environment organization
239  */
240 
241 /* **** PISMO SUPPORT *** */
242 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
243 #define CONFIG_NAND_OMAP_GPMC
244 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
245 
246 /* Redundant Environment */
247 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
248 #define CONFIG_ENV_OFFSET		0x180000
249 #define CONFIG_ENV_ADDR			0x180000
250 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
251 						2 * CONFIG_SYS_ENV_SECT_SIZE)
252 #define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
253 
254 /* Flash banks JFFS2 should use */
255 #define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
256 					CONFIG_SYS_MAX_NAND_DEVICE)
257 #define CONFIG_SYS_JFFS2_MEM_NAND
258 /* use flash_info[2] */
259 #define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
260 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
261 
262 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
263 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
264 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
265 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
266 					 CONFIG_SYS_INIT_RAM_SIZE - \
267 					 GENERATED_GBL_DATA_SIZE)
268 
269 /* Defines for SPL */
270 #define CONFIG_SPL_FRAMEWORK
271 #define CONFIG_SPL_NAND_SIMPLE
272 
273 #define CONFIG_SPL_NAND_BASE
274 #define CONFIG_SPL_NAND_DRIVERS
275 #define CONFIG_SPL_NAND_ECC
276 
277 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
278 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
279 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
280 
281 /* move malloc and bss high to prevent clashing with the main image */
282 #define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
283 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
284 #define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
285 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
286 
287 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
288 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
289 
290 /* NAND boot config */
291 #define CONFIG_SYS_NAND_PAGE_COUNT	64
292 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
293 #define CONFIG_SYS_NAND_OOBSIZE		64
294 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
295 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
296 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
297 #define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
298 					 48, 49, 50, 51, 52, 53, 54, 55,\
299 					 56, 57, 58, 59, 60, 61, 62, 63}
300 #define CONFIG_SYS_NAND_ECCSIZE		256
301 #define CONFIG_SYS_NAND_ECCBYTES	3
302 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
303 #define CONFIG_SPL_NAND_SOFTECC
304 
305 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
306 
307 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
308 
309 /*
310  * ethernet support
311  *
312  */
313 #if defined(CONFIG_CMD_NET)
314 #define CONFIG_DRIVER_TI_EMAC
315 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
316 #define CONFIG_MII
317 #define CONFIG_BOOTP_DNS
318 #define CONFIG_BOOTP_DNS2
319 #define CONFIG_BOOTP_SEND_HOSTNAME
320 #define CONFIG_NET_RETRY_COUNT 10
321 #endif
322 
323 #define CONFIG_SPLASH_SCREEN
324 #define CONFIG_VIDEO_BMP_RLE8
325 #define CONFIG_VIDEO_OMAP3
326 
327 #endif /* __CONFIG_H */
328