1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on omap3_evm_config.h 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_OMAP /* in a TI OMAP core */ 16 #define CONFIG_OMAP3_MCX /* working with mcx */ 17 #define CONFIG_OMAP_GPIO 18 /* Common ARM Erratas */ 19 #define CONFIG_ARM_ERRATA_454179 20 #define CONFIG_ARM_ERRATA_430973 21 #define CONFIG_ARM_ERRATA_621766 22 23 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 24 25 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 26 27 #include <asm/arch/cpu.h> /* get chip and board defs */ 28 #include <asm/arch/omap.h> 29 30 /* 31 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 32 * and older u-boot.bin with the new U-Boot SPL. 33 */ 34 #define CONFIG_SYS_TEXT_BASE 0x80008000 35 36 /* Clock Defines */ 37 #define V_OSCK 26000000 /* Clock output from T2 */ 38 #define V_SCLK (V_OSCK >> 1) 39 40 #define CONFIG_MISC_INIT_R 41 42 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 43 #define CONFIG_SETUP_MEMORY_TAGS 44 #define CONFIG_INITRD_TAG 45 #define CONFIG_REVISION_TAG 46 47 /* 48 * Size of malloc() pool 49 */ 50 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 51 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 52 /* 53 * DDR related 54 */ 55 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 56 57 /* 58 * Hardware drivers 59 */ 60 61 /* 62 * NS16550 Configuration 63 */ 64 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 65 66 #define CONFIG_SYS_NS16550_SERIAL 67 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 68 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 69 70 /* 71 * select serial console configuration 72 */ 73 #define CONFIG_CONS_INDEX 3 74 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 75 #define CONFIG_SERIAL3 3 /* UART3 */ 76 77 /* allow to overwrite serial and ethaddr */ 78 #define CONFIG_ENV_OVERWRITE 79 #define CONFIG_BAUDRATE 115200 80 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 81 115200} 82 83 /* EHCI */ 84 #define CONFIG_OMAP3_GPIO_2 85 #define CONFIG_OMAP3_GPIO_5 86 #define CONFIG_USB_EHCI 87 #define CONFIG_USB_EHCI_OMAP 88 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 89 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 90 #define CONFIG_USB_HOST_ETHER 91 #define CONFIG_USB_ETHER_ASIX 92 #define CONFIG_USB_ETHER_MCS7830 93 94 /* commands to include */ 95 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 96 97 #define CONFIG_CMD_DATE 98 #define CONFIG_CMD_NAND /* NAND support */ 99 #define CONFIG_CMD_UBIFS 100 #define CONFIG_RBTREE 101 #define CONFIG_LZO 102 #define CONFIG_MTD_PARTITIONS 103 #define CONFIG_MTD_DEVICE 104 #define CONFIG_CMD_MTDPARTS 105 106 #define CONFIG_SYS_NO_FLASH 107 #define CONFIG_SYS_I2C 108 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 109 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 110 #define CONFIG_SYS_I2C_OMAP34XX 111 112 /* RTC */ 113 #define CONFIG_RTC_DS1337 114 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 115 116 /* 117 * Board NAND Info. 118 */ 119 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 120 /* to access nand */ 121 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 122 /* to access */ 123 /* nand at CS0 */ 124 125 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 126 /* NAND devices */ 127 #define CONFIG_JFFS2_NAND 128 /* nand device jffs2 lives on */ 129 #define CONFIG_JFFS2_DEV "nand0" 130 /* start of jffs2 partition */ 131 #define CONFIG_JFFS2_PART_OFFSET 0x680000 132 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 133 134 /* Environment information */ 135 136 #define CONFIG_BOOTFILE "uImage" 137 138 /* Setup MTD for NAND on the SOM */ 139 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 140 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 141 "1m(u-boot),256k(env1)," \ 142 "256k(env2),6m(kernel),6m(k_recovery)," \ 143 "8m(fs_recovery),-(common_data)" 144 145 #define CONFIG_HOSTNAME mcx 146 #define CONFIG_EXTRA_ENV_SETTINGS \ 147 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 148 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 149 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 150 "addfb=setenv bootargs ${bootargs} vram=6M " \ 151 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 152 "addip_sta=setenv bootargs ${bootargs} " \ 153 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 154 "${netmask}:${hostname}:eth0:off\0" \ 155 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 156 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 157 "else run addip_sta;fi\0" \ 158 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 159 "addtty=setenv bootargs ${bootargs} " \ 160 "console=${consoledev},${baudrate}\0" \ 161 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 162 "baudrate=115200\0" \ 163 "consoledev=ttyO2\0" \ 164 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 165 "loadaddr=0x82000000\0" \ 166 "load=tftp ${loadaddr} ${u-boot}\0" \ 167 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 168 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 169 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 170 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 171 "mmcargs=root=/dev/mmcblk0p2 rw " \ 172 "rootfstype=ext3 rootwait\0" \ 173 "mmcboot=echo Booting from mmc ...; " \ 174 "run mmcargs; " \ 175 "run addip addtty addmtd addfb addeth addmisc;" \ 176 "run loaduimage; " \ 177 "bootm ${loadaddr}\0" \ 178 "net_nfs=run load_k; " \ 179 "run nfsargs; " \ 180 "run addip addtty addmtd addfb addeth addmisc;" \ 181 "bootm ${loadaddr}\0" \ 182 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 183 "nfsroot=${serverip}:${rootpath}\0" \ 184 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 185 "uboot_addr=0x80000\0" \ 186 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 187 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 188 "updatemlo=nandecc hw;nand erase 0 20000;" \ 189 "nand write ${loadaddr} 0 20000\0" \ 190 "upd=if run load;then echo Updating u-boot;if run update;" \ 191 "then echo U-Boot updated;" \ 192 "else echo Error updating u-boot !;" \ 193 "echo Board without bootloader !!;" \ 194 "fi;" \ 195 "else echo U-Boot not downloaded..exiting;fi\0" \ 196 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 197 "bootscript=echo Running bootscript from mmc ...; " \ 198 "source ${loadaddr}\0" \ 199 "nandargs=setenv bootargs ubi.mtd=7 " \ 200 "root=ubi0:rootfs rootfstype=ubifs\0" \ 201 "nandboot=echo Booting from nand ...; " \ 202 "run nandargs; " \ 203 "ubi part nand0,4;" \ 204 "ubi readvol ${loadaddr} kernel;" \ 205 "run addtty addmtd addfb addeth addmisc;" \ 206 "bootm ${loadaddr}\0" \ 207 "preboot=ubi part nand0,7;" \ 208 "ubi readvol ${loadaddr} splash;" \ 209 "bmp display ${loadaddr};" \ 210 "gpio set 55\0" \ 211 "swupdate_args=setenv bootargs root=/dev/ram " \ 212 "quiet loglevel=1 " \ 213 "consoleblank=0 ${swupdate_misc}\0" \ 214 "swupdate=echo Running Sw-Update...;" \ 215 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 216 "else mtdparts default;fi; " \ 217 "ubi part nand0,5;" \ 218 "ubi readvol 0x82000000 kernel_recovery;" \ 219 "ubi part nand0,6;" \ 220 "ubi readvol 0x84000000 fs_recovery;" \ 221 "run swupdate_args; " \ 222 "setenv bootargs ${bootargs} " \ 223 "${mtdparts} " \ 224 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 225 "omapdss.def_disp=lcd;" \ 226 "bootm 0x82000000 0x84000000\0" \ 227 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 228 "then source 82000000;else run nandboot;fi\0" 229 230 #define CONFIG_AUTO_COMPLETE 231 #define CONFIG_CMDLINE_EDITING 232 233 /* 234 * Miscellaneous configurable options 235 */ 236 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 237 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 238 /* Print Buffer Size */ 239 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 240 sizeof(CONFIG_SYS_PROMPT) + 16) 241 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 242 /* args */ 243 /* Boot Argument Buffer Size */ 244 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 245 /* memtest works on */ 246 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 247 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 248 0x01F00000) /* 31MB */ 249 250 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 251 /* address */ 252 #define CONFIG_PREBOOT 253 254 /* 255 * AM3517 has 12 GP timers, they can be driven by the system clock 256 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 257 * This rate is divided by a local divisor. 258 */ 259 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 260 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 261 262 /* 263 * Physical Memory Map 264 */ 265 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 266 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 267 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 268 269 /* 270 * FLASH and environment organization 271 */ 272 273 /* **** PISMO SUPPORT *** */ 274 #define CONFIG_NAND 275 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 276 #define CONFIG_NAND_OMAP_GPMC 277 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 278 #define CONFIG_ENV_IS_IN_NAND 279 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 280 281 /* Redundant Environment */ 282 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 283 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 284 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 285 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 286 2 * CONFIG_SYS_ENV_SECT_SIZE) 287 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 288 289 /* Flash banks JFFS2 should use */ 290 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 291 CONFIG_SYS_MAX_NAND_DEVICE) 292 #define CONFIG_SYS_JFFS2_MEM_NAND 293 /* use flash_info[2] */ 294 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 295 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 296 297 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 298 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 299 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 300 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 301 CONFIG_SYS_INIT_RAM_SIZE - \ 302 GENERATED_GBL_DATA_SIZE) 303 304 /* Defines for SPL */ 305 #define CONFIG_SPL_FRAMEWORK 306 #define CONFIG_SPL_BOARD_INIT 307 #define CONFIG_SPL_NAND_SIMPLE 308 309 #define CONFIG_SPL_NAND_BASE 310 #define CONFIG_SPL_NAND_DRIVERS 311 #define CONFIG_SPL_NAND_ECC 312 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 313 314 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 315 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 316 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 317 318 /* move malloc and bss high to prevent clashing with the main image */ 319 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 320 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 321 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 322 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 323 324 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 325 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 326 327 /* NAND boot config */ 328 #define CONFIG_SYS_NAND_PAGE_COUNT 64 329 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 330 #define CONFIG_SYS_NAND_OOBSIZE 64 331 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 332 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 333 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 334 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 335 48, 49, 50, 51, 52, 53, 54, 55,\ 336 56, 57, 58, 59, 60, 61, 62, 63} 337 #define CONFIG_SYS_NAND_ECCSIZE 256 338 #define CONFIG_SYS_NAND_ECCBYTES 3 339 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 340 #define CONFIG_SPL_NAND_SOFTECC 341 342 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 343 344 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 345 346 /* 347 * ethernet support 348 * 349 */ 350 #if defined(CONFIG_CMD_NET) 351 #define CONFIG_DRIVER_TI_EMAC 352 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 353 #define CONFIG_MII 354 #define CONFIG_BOOTP_DNS 355 #define CONFIG_BOOTP_DNS2 356 #define CONFIG_BOOTP_SEND_HOSTNAME 357 #define CONFIG_NET_RETRY_COUNT 10 358 #endif 359 360 #define CONFIG_SPLASH_SCREEN 361 #define CONFIG_VIDEO_BMP_RLE8 362 #define CONFIG_CMD_BMP 363 #define CONFIG_VIDEO_OMAP3 364 365 #endif /* __CONFIG_H */ 366