1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on omap3_evm_config.h 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 16 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 17 18 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 19 20 #include <asm/arch/cpu.h> /* get chip and board defs */ 21 #include <asm/arch/omap.h> 22 23 /* 24 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 25 * and older u-boot.bin with the new U-Boot SPL. 26 */ 27 #define CONFIG_SYS_TEXT_BASE 0x80008000 28 29 /* Clock Defines */ 30 #define V_OSCK 26000000 /* Clock output from T2 */ 31 #define V_SCLK (V_OSCK >> 1) 32 33 #define CONFIG_MISC_INIT_R 34 35 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 36 #define CONFIG_SETUP_MEMORY_TAGS 37 #define CONFIG_INITRD_TAG 38 #define CONFIG_REVISION_TAG 39 40 /* 41 * Size of malloc() pool 42 */ 43 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 44 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 45 /* 46 * DDR related 47 */ 48 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 49 50 /* 51 * Hardware drivers 52 */ 53 54 /* 55 * NS16550 Configuration 56 */ 57 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 58 59 #define CONFIG_SYS_NS16550_SERIAL 60 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 61 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 62 63 /* 64 * select serial console configuration 65 */ 66 #define CONFIG_CONS_INDEX 3 67 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 68 #define CONFIG_SERIAL3 3 /* UART3 */ 69 70 /* allow to overwrite serial and ethaddr */ 71 #define CONFIG_ENV_OVERWRITE 72 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 73 115200} 74 75 /* EHCI */ 76 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 77 #define CONFIG_USB_HOST_ETHER 78 #define CONFIG_USB_ETHER_ASIX 79 #define CONFIG_USB_ETHER_MCS7830 80 81 /* commands to include */ 82 83 #define CONFIG_MTD_PARTITIONS 84 #define CONFIG_MTD_DEVICE 85 86 #define CONFIG_SYS_I2C 87 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 88 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 89 90 /* RTC */ 91 #define CONFIG_RTC_DS1337 92 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 93 94 /* 95 * Board NAND Info. 96 */ 97 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 98 /* to access nand */ 99 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 100 /* to access */ 101 /* nand at CS0 */ 102 103 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 104 /* NAND devices */ 105 #define CONFIG_JFFS2_NAND 106 /* nand device jffs2 lives on */ 107 #define CONFIG_JFFS2_DEV "nand0" 108 /* start of jffs2 partition */ 109 #define CONFIG_JFFS2_PART_OFFSET 0x680000 110 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 111 112 /* Environment information */ 113 114 #define CONFIG_BOOTFILE "uImage" 115 116 /* Setup MTD for NAND on the SOM */ 117 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 118 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 119 "1m(u-boot),256k(env1)," \ 120 "256k(env2),6m(kernel),6m(k_recovery)," \ 121 "8m(fs_recovery),-(common_data)" 122 123 #define CONFIG_HOSTNAME mcx 124 #define CONFIG_EXTRA_ENV_SETTINGS \ 125 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 126 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 127 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 128 "addfb=setenv bootargs ${bootargs} vram=6M " \ 129 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 130 "addip_sta=setenv bootargs ${bootargs} " \ 131 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 132 "${netmask}:${hostname}:eth0:off\0" \ 133 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 134 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 135 "else run addip_sta;fi\0" \ 136 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 137 "addtty=setenv bootargs ${bootargs} " \ 138 "console=${consoledev},${baudrate}\0" \ 139 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 140 "baudrate=115200\0" \ 141 "consoledev=ttyO2\0" \ 142 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 143 "loadaddr=0x82000000\0" \ 144 "load=tftp ${loadaddr} ${u-boot}\0" \ 145 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 146 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 147 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 148 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 149 "mmcargs=root=/dev/mmcblk0p2 rw " \ 150 "rootfstype=ext3 rootwait\0" \ 151 "mmcboot=echo Booting from mmc ...; " \ 152 "run mmcargs; " \ 153 "run addip addtty addmtd addfb addeth addmisc;" \ 154 "run loaduimage; " \ 155 "bootm ${loadaddr}\0" \ 156 "net_nfs=run load_k; " \ 157 "run nfsargs; " \ 158 "run addip addtty addmtd addfb addeth addmisc;" \ 159 "bootm ${loadaddr}\0" \ 160 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 161 "nfsroot=${serverip}:${rootpath}\0" \ 162 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 163 "uboot_addr=0x80000\0" \ 164 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 165 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 166 "updatemlo=nandecc hw;nand erase 0 20000;" \ 167 "nand write ${loadaddr} 0 20000\0" \ 168 "upd=if run load;then echo Updating u-boot;if run update;" \ 169 "then echo U-Boot updated;" \ 170 "else echo Error updating u-boot !;" \ 171 "echo Board without bootloader !!;" \ 172 "fi;" \ 173 "else echo U-Boot not downloaded..exiting;fi\0" \ 174 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 175 "bootscript=echo Running bootscript from mmc ...; " \ 176 "source ${loadaddr}\0" \ 177 "nandargs=setenv bootargs ubi.mtd=7 " \ 178 "root=ubi0:rootfs rootfstype=ubifs\0" \ 179 "nandboot=echo Booting from nand ...; " \ 180 "run nandargs; " \ 181 "ubi part nand0,4;" \ 182 "ubi readvol ${loadaddr} kernel;" \ 183 "run addtty addmtd addfb addeth addmisc;" \ 184 "bootm ${loadaddr}\0" \ 185 "preboot=ubi part nand0,7;" \ 186 "ubi readvol ${loadaddr} splash;" \ 187 "bmp display ${loadaddr};" \ 188 "gpio set 55\0" \ 189 "swupdate_args=setenv bootargs root=/dev/ram " \ 190 "quiet loglevel=1 " \ 191 "consoleblank=0 ${swupdate_misc}\0" \ 192 "swupdate=echo Running Sw-Update...;" \ 193 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 194 "else mtdparts default;fi; " \ 195 "ubi part nand0,5;" \ 196 "ubi readvol 0x82000000 kernel_recovery;" \ 197 "ubi part nand0,6;" \ 198 "ubi readvol 0x84000000 fs_recovery;" \ 199 "run swupdate_args; " \ 200 "setenv bootargs ${bootargs} " \ 201 "${mtdparts} " \ 202 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 203 "omapdss.def_disp=lcd;" \ 204 "bootm 0x82000000 0x84000000\0" \ 205 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 206 "then source 82000000;else run nandboot;fi\0" 207 208 #define CONFIG_AUTO_COMPLETE 209 #define CONFIG_CMDLINE_EDITING 210 211 /* 212 * Miscellaneous configurable options 213 */ 214 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 215 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 216 /* Print Buffer Size */ 217 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 218 sizeof(CONFIG_SYS_PROMPT) + 16) 219 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 220 /* args */ 221 /* Boot Argument Buffer Size */ 222 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 223 /* memtest works on */ 224 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 225 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 226 0x01F00000) /* 31MB */ 227 228 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 229 /* address */ 230 #define CONFIG_PREBOOT 231 232 /* 233 * AM3517 has 12 GP timers, they can be driven by the system clock 234 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 235 * This rate is divided by a local divisor. 236 */ 237 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 238 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 239 240 /* 241 * Physical Memory Map 242 */ 243 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 244 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 245 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 246 247 /* 248 * FLASH and environment organization 249 */ 250 251 /* **** PISMO SUPPORT *** */ 252 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 253 #define CONFIG_NAND_OMAP_GPMC 254 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 255 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 256 257 /* Redundant Environment */ 258 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 259 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 260 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 261 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 262 2 * CONFIG_SYS_ENV_SECT_SIZE) 263 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 264 265 /* Flash banks JFFS2 should use */ 266 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 267 CONFIG_SYS_MAX_NAND_DEVICE) 268 #define CONFIG_SYS_JFFS2_MEM_NAND 269 /* use flash_info[2] */ 270 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 271 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 272 273 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 274 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 275 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 276 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 277 CONFIG_SYS_INIT_RAM_SIZE - \ 278 GENERATED_GBL_DATA_SIZE) 279 280 /* Defines for SPL */ 281 #define CONFIG_SPL_FRAMEWORK 282 #define CONFIG_SPL_NAND_SIMPLE 283 284 #define CONFIG_SPL_NAND_BASE 285 #define CONFIG_SPL_NAND_DRIVERS 286 #define CONFIG_SPL_NAND_ECC 287 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 288 289 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 290 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 291 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 292 293 /* move malloc and bss high to prevent clashing with the main image */ 294 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 295 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 296 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 297 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 298 299 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 300 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 301 302 /* NAND boot config */ 303 #define CONFIG_SYS_NAND_PAGE_COUNT 64 304 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 305 #define CONFIG_SYS_NAND_OOBSIZE 64 306 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 307 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 308 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 309 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 310 48, 49, 50, 51, 52, 53, 54, 55,\ 311 56, 57, 58, 59, 60, 61, 62, 63} 312 #define CONFIG_SYS_NAND_ECCSIZE 256 313 #define CONFIG_SYS_NAND_ECCBYTES 3 314 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 315 #define CONFIG_SPL_NAND_SOFTECC 316 317 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 318 319 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 320 321 /* 322 * ethernet support 323 * 324 */ 325 #if defined(CONFIG_CMD_NET) 326 #define CONFIG_DRIVER_TI_EMAC 327 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 328 #define CONFIG_MII 329 #define CONFIG_BOOTP_DNS 330 #define CONFIG_BOOTP_DNS2 331 #define CONFIG_BOOTP_SEND_HOSTNAME 332 #define CONFIG_NET_RETRY_COUNT 10 333 #endif 334 335 #define CONFIG_SPLASH_SCREEN 336 #define CONFIG_VIDEO_BMP_RLE8 337 #define CONFIG_VIDEO_OMAP3 338 339 #endif /* __CONFIG_H */ 340